IC封装与SiP 设计 

物理版图和协同设计 SiP和复杂的IC封装设计需要在芯片和封装之间进行无缝集成。Cadence®物理版图和协同技术能够提供强大的建模与仿真，以支持在设计初期充分了解各项信息后实现设计权衡。

Allegro Package Designer

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die or side by side die designs.

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Cadence 3D Design Viewer

Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.

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信号完整性(SI)分析和建模 信号完整性和封装特征化对于评估设计对系统性能的影响来说至关重要。Cadence®技术提供了集成的SI分析、建模和仿真，以便在控制进度和成本的同时验证设计质量。

Allegro Package SI

Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions.

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Cadence SiP Digital SI

Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects.

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数字系统级封装(SiP)设计 系统级封装(SiP)开发要基于网络的互连关系直接与芯片团队进行协同设计。Cadence®解决方案提供了I/O优化、均衡仿真和约束驱动的实现。

Cadence SiP Digital Architect

Enables experimentation at the initial design stages for maximum functional density and performance. Evaluates tradeoffs and provides co-design optimization of IC I/O padring/array. Optimized for co-design with Encounter Digital Implementation System.

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Cadence SiP Layout

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die, side by side die, and stacked die designs and also provides the foundation for chip-package co-design with Encounter or Virtuoso.

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Cadence SiP Digital SI

Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects.

了解更多 »

Cadence SiP Co-Design

Flexible chip-package co-design methodologies with supporting utilities allow for customizable co-design flows that meet the organizational challenges associated with collaboration between chip and package design teams that may be globally distributed.

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模拟和射频(RF)系统级封装(SiP)设计 手持设备中的混合信号应用推动了系统级封装(SiP)设计，但是RF集成会影响性能。Cadence®模拟和射频(RF)系统级封装(SiP)设计从芯片设计数据入手，支持封装级仿真、优化和验证。

Cadence Virtuoso SiP Architect

Delivers a single schematic and simulation solution for RF/analog ICs and complex IC package substrates. Supports package substrate-level passive structures based on Pcell technology. Also enables chip-package co-design with Virtuoso.

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Cadence SiP Layout

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die, side by side die, and stacked die designs and also provides the foundation for chip-package co-design with Encounter or Virtuoso.

了解更多 »

Cadence SiP Co-Design

Flexible chip-package co-design methodologies with supporting utilities allow for customizable co-design flows that meet the organizational challenges associated with collaboration between chip and package design teams that may be globally distributed.

了解更多 »

Allegro Package Designer

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die or side by side die designs.

了解更多 »

Allegro Package SI

Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions.

了解更多 »

Cadence 3D Design Viewer

Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.

了解更多 »

Cadence SiP Co-Design

Flexible chip-package co-design methodologies with supporting utilities allow for customizable co-design flows that meet the organizational challenges associated with collaboration between chip and package design teams that may be globally distributed.

了解更多 »

Cadence SiP Digital Architect

Enables experimentation at the initial design stages for maximum functional density and performance. Evaluates tradeoffs and provides co-design optimization of IC I/O padring/array. Optimized for co-design with Encounter Digital Implementation System.

了解更多 »

Cadence SiP Digital SI

Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects.

了解更多 »

Cadence SiP Layout

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die, side by side die, and stacked die designs and also provides the foundation for chip-package co-design with Encounter or Virtuoso.

了解更多 »

Cadence Virtuoso SiP Architect

Delivers a single schematic and simulation solution for RF/analog ICs and complex IC package substrates. Supports package substrate-level passive structures based on Pcell technology. Also enables chip-package co-design with Virtuoso.

了解更多 »