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IC封装与SiP 设计 

Press Releases
Cadence SiP Technologies and Allegro Package Designer Optimized for Hand-Held Consumer Electronics Market
IC Package Designers Boost Productivity with New Cadence Allegro SiP and IC Packaging Software
Cadence Extends Performance Leadership with Expanded Multi-Core Support

Multi-Fabric Planning for Efficient PCB Design
3D packaging takes a key step forward as TSMC tapes out CoWoS chips
IC Package prototyping methodology estimates feasibility and cost

Japan Electronics Packaging and Circuits Association (JPCA) Show
06/03/2015 - Tokyo
DAC 2015
06/07/2015 - Moscone Center, San Francisco
CDNLive Korea
07/15/2015 - Seoul

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