PCB 设计 

PCB前端设计 Front-End的PCB设计，针对各个方面的规则约束，需要有明确的设定。Cadence®技术支持基于准确的仿真结果，权衡不同设计需求，来满足上述的设计要求。

Allegro Design Authoring

Provides a multi-style logic authoring-driven, constraint-driven flow. Manages design constraints, net classes, buses, extended nets, and differential pairs.

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Allegro Design Entry Capture / Capture CIS

Enables rapid, intuitive schematic editing and hierarchical design with optimized sharing and reuse of components and subassemblies. Automates integration of field programmable gate arrays (FPGAs) and programmable logic devices (PLDs).

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Allegro Design Publisher

Converts Allegro Design Authoring schematics and Allegro PCB Designer PCBs to content-rich PDFs—creating a secure, single-file representation of the design.

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Cadence OrCAD Capture / Capture CIS

Offers full-featured schematic editing of complex designs through hierarchical and variant design capabilities for fast, intuitive design capture. Robust component information system (CIS) promotes use of preferred, current parts to accelerate design capture and reduce project costs.

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FPGA-PCB协同设计 在大规模管脚数目的FPGA设计中，有很多各种类型的规则约束，用于FPGA的管脚分配的。基于约束的管脚分配，传统的方法是以人工的方式来进行的。用这样的方法在PCB上做管脚再分配，会产生很多无效的分配，和错误的分配，从而影响了设计的周期和进度。Cadence用基于约束的自动管脚分配，以及双向协同布局的产品，替代了传统容易出错的人工分配的方式。

Allegro FPGA System Planner

The Allegro FPGA System Planner offers a complete, scalable technology for FPGA-PCB co-design that allows users to automatically create an optimum placement-aware initial pin assignment for one or more FPGAs.  It also allows users to optimize pin assignment after placement or during routing of signals on the PCB.

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Cadence OrCAD FPGA System Planner

The OrCAD FPGA System Planner offers technology for FPGA-PCB co-design that allows users to automatically create an optimum placement-aware initial pin assignment for an FPGA.

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模拟混合信号仿真 在投板之前，利用准确的仿真可以提早发现设计的问题，从而节省时间和预算。Cadence®模拟/混合信号(AMS)仿真器，支持准确的元件建模、设计的验证和优化，从而降低设计的缺陷与风险。

Allegro AMS Simulator

Delivers advanced simulation capabilities for analog/mixed-signal development. Provides design entry feedback, component modeling, stress analysis, and yield projections.

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Cadence PSpice A/D and Advanced Analysis

Simulates analog/mixed-signal circuits quickly and completely to improve productivity and data integrity. Advanced Analysis prevents board failures by determining which components are over-stressed using Smoke analysis or by observing component yields using Monte Carlo analysis.

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版图设计与布线 一再缩短的设计周期和带有约束的网段数量的不断增加要求客户采用PCB设计方法，该方法能够提高可预见性，并加快设计周转时间。Cadence®版图设计与布线技术提供了可扩展、易用并且由约束驱动的PCB设计解决方案，适用于简单到复杂的PCB设计，包括带有RF Etch组件的情况。

Allegro PCB Designer

Speeds designs from placement and routing through to manufacturing with powerful features such as design partitioning, RF design capabilities, and interconnect design planning. Production-proven to increase productivity and help engineers quickly ramp up to volume production.

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Cadence OrCAD PCB Designer

Offers a proven, scalable, easy-to-use PCB editing and routing solution. Delivers a comprehensive feature set and seamless PCB design environment to take designs from concept to production.

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信号完整性与电源完整性 越来越高的频率，越来越复杂及越来越小的设计，给信号完整性及电源完整性带来了越来越高的要求。Cadence®信号完整性与电源完整性技术，概含从单一电子元件分析，到多板互联分析。并且支持数GHz频率范围。

Allegro PCB SI

Provides advanced interconnect modeling for constraint development and electrical analysis of multi-gigabit designs. Simulates high-speed signals, systems, and power delivery networks at the single- or multi-board level.

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Cadence OrCAD PCB SI

Provides detailed interconnect modeling and electrical analysis. Enables pre- and post-layout signal integrity analysis at any stage.

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库和设计数据管理 桌面访问方式的组件信息，对于设计数据，设计的成本以及即时的设计进度来说，至关重要。Cadence®库和设计数据管理系统，提供了用于公司的设计流程管理，成本控制以及各方面协同的数据链方式。

Allegro Design Workbench

Provides a collaborative environment that integrates design tools, library development and distribution, data management, and process control—all aimed at increasing productivity, reducing errors, and eliminating redundancy.

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Allegro PCB Librarian

Significantly accelerates creation and validation of schematic, PCB footprint and digital simulation map files. This enables librarians, engineers and/or designers to reduce development time for high-pin-count devices from days to minutes.

了解更多 »

Allegro AMS Simulator

Delivers advanced simulation capabilities for analog/mixed-signal development. Provides design entry feedback, component modeling, stress analysis, and yield projections.

了解更多 »

Allegro Design Authoring

Provides a multi-style logic authoring-driven, constraint-driven flow. Manages design constraints, net classes, buses, extended nets, and differential pairs.

了解更多 »

Allegro Design Entry Capture / Capture CIS

Enables rapid, intuitive schematic editing and hierarchical design with optimized sharing and reuse of components and subassemblies. Automates integration of field programmable gate arrays (FPGAs) and programmable logic devices (PLDs).

了解更多 »

Allegro Design Publisher

Converts Allegro Design Authoring schematics and Allegro PCB Designer PCBs to content-rich PDFs—creating a secure, single-file representation of the design.

了解更多 »

Allegro Design Workbench

Provides a collaborative environment that integrates design tools, library development and distribution, data management, and process control—all aimed at increasing productivity, reducing errors, and eliminating redundancy.

了解更多 »

Allegro FPGA System Planner

The Allegro FPGA System Planner offers a complete, scalable technology for FPGA-PCB co-design that allows users to automatically create an optimum placement-aware initial pin assignment for one or more FPGAs.  It also allows users to optimize pin assignment after placement or during routing of signals on the PCB.

了解更多 »

Allegro PCB Designer

Speeds designs from placement and routing through to manufacturing with powerful features such as design partitioning, RF design capabilities, and interconnect design planning. Production-proven to increase productivity and help engineers quickly ramp up to volume production.

了解更多 »

Allegro PCB Librarian

Significantly accelerates creation and validation of schematic, PCB footprint and digital simulation map files. This enables librarians, engineers and/or designers to reduce development time for high-pin-count devices from days to minutes.

了解更多 »

Allegro PCB SI

Provides advanced interconnect modeling for constraint development and electrical analysis of multi-gigabit designs. Simulates high-speed signals, systems, and power delivery networks at the single- or multi-board level.

了解更多 »

Cadence OrCAD Capture / Capture CIS

Offers full-featured schematic editing of complex designs through hierarchical and variant design capabilities for fast, intuitive design capture. Robust component information system (CIS) promotes use of preferred, current parts to accelerate design capture and reduce project costs.

了解更多 »

Cadence OrCAD FPGA System Planner

The OrCAD FPGA System Planner offers technology for FPGA-PCB co-design that allows users to automatically create an optimum placement-aware initial pin assignment for an FPGA.

了解更多 »

Cadence OrCAD PCB Designer

Offers a proven, scalable, easy-to-use PCB editing and routing solution. Delivers a comprehensive feature set and seamless PCB design environment to take designs from concept to production.

了解更多 »

Cadence OrCAD PCB SI

Provides detailed interconnect modeling and electrical analysis. Enables pre- and post-layout signal integrity analysis at any stage.

了解更多 »

Cadence PSpice A/D and Advanced Analysis

Simulates analog/mixed-signal circuits quickly and completely to improve productivity and data integrity. Advanced Analysis prevents board failures by determining which components are over-stressed using Smoke analysis or by observing component yields using Monte Carlo analysis.

了解更多 »