可制造性签收 

面向光刻的设计 随着45纳米工艺技术的普及，在SoC、ASIC和全定制设计中必须将芯片制造中因光刻工艺而产生的系统性变化考虑在内。Cadence®面向光刻的设计解决方案能够帮助设计者防止在布线期间因光刻而导致的严重后果，并调用代工厂认证的、基于模型的解决方案对此进行监测，实现自动化修复。从而确保设计在芯片中得到完全实现，设计团队能够最大化芯片成品率，提高芯片性能，并避免出现耗费巨大的芯片重启。

Cadence Litho Physical Analyzer

Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.

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Cadence Litho Electrical Analyzer

Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.

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面向CMP的设计 因化学机械抛光(CMP)产生的厚度变化可能引起芯片的物理故障或电气故障，需要在芯片制造之前对其进行分析。Cadence®面向CMP的设计技术提供了一种基于模型的方法，能够精确地预测众多层次的厚度变化。通过使用智能填充和并发多角时序优化方法，设计者能够提前评估CMP对其设计的影响，从而最小化物理故障和电气故障对芯片成品率的影响。

Cadence CMP Predictor

Enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction.

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物理验证 物理验证通常包含设计规则检查(DRC)和版图与逻辑设计一致性验证(LVS)，它能够确保代工厂给出的空间和其他物理规则在指定版图设计中得到遵守。Cadence®物理验证技术支持快速、精确、代工厂认证的DRC和LVS，支持任何设计类型，包括标准元件、IP、模块或完整芯片。

Cadence Physical Verification System

Offers a front-to-back design, implementation, and signoff flow in a single solution. Speeds turnaround of design rule check and layout versus schematic verification.

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Assura Physical Verification

Performs design rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.

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芯片优化 传统的IC实现工具只会为互连线创建过度简化的模型。Cadence®芯片优化技术使用一种创新的基于空间的模型，它能够满足亚波长光刻和制造工艺规则的绝大多数要求。它基于电气约束、制造规则和时序目标来优化版图设计，从而提高芯片的可制造性、成品率和性能。

Cadence Chip Optimizer

Uses a 3D space-based approach that models, analyzes, and optimizes layout based on electrical constraints, manufacturing rules, and objectives.

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Encounter Diagnostics

Delivers the most accurate volume and precision diagnostics capability available on the market. Accelerates silicon bring-up and optimizes yield ramp with device and fault modeling.

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良率分析与诊断 在90nm以下工艺中，芯片良率下降已经成为最重要的挑战之一。传统的在线检测技术已经跟不上由于精细设计工艺中存在的不确定性而产生的缺陷类型的增长。Cadence 提供业界第一个良率分析与诊断平台，并已证明能加速提高芯片制造良率。它能够快速有效地分析成千上万的故障点，确定引起良率下降的根源，并且能够精确定位在网表与版图中的位置，从而提高芯片的可制造型与良率。

Encounter Diagnostics

Delivers the most accurate volume and precision diagnostics capability available on the market. Accelerates silicon bring-up and optimizes yield ramp with device and fault modeling.

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Encounter Digital Implementation System

Encounter Digital Implementation System delivers a complete solution for variation- and manufacturing-aware design closure, low power, mixed-signal implementation, and integrated signoff in a single, scalable multi-CPU-enabled design environment for high-capacity, high-performance digital implementation.

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掩模数据准备 为了在流片过程中提高生产速度并减少错误，工程师需要最新的分辨力增强技术(RET)和光学邻近修正(OPC)功能。Cadence®技术提供了面向OPC的先进并发工艺和邻近补偿解决方案，以及业内使用最广泛的MAST数据准备和芯片分析解决方案，经领先的代工厂认可适用于所有纳米工艺节点。

Cadence MaskCompose Reticle and Wafer Synthesis Suite

Automates and optimizes reticle and wafer synthesis to eliminate errors and reduce mask-making cycle times.

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Cadence QuickView Layout and Manufacturing Data Viewer

Allows engineers to view and superimpose manufacturing data in various industry-standard formats.

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Assura Physical Verification

Performs design rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.

了解更多 »

Cadence Chip Optimizer

Uses a 3D space-based approach that models, analyzes, and optimizes layout based on electrical constraints, manufacturing rules, and objectives.

了解更多 »

Cadence CMP Predictor

Enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction.

了解更多 »

Cadence Litho Electrical Analyzer

Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.

了解更多 »

Cadence Litho Physical Analyzer

Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.

了解更多 »

Cadence MaskCompose Reticle and Wafer Synthesis Suite

Automates and optimizes reticle and wafer synthesis to eliminate errors and reduce mask-making cycle times.

了解更多 »

Cadence Physical Verification System

Offers a front-to-back design, implementation, and signoff flow in a single solution. Speeds turnaround of design rule check and layout versus schematic verification.

了解更多 »

Cadence QuickView Layout and Manufacturing Data Viewer

Allows engineers to view and superimpose manufacturing data in various industry-standard formats.

了解更多 »

Encounter Diagnostics

Delivers the most accurate volume and precision diagnostics capability available on the market. Accelerates silicon bring-up and optimizes yield ramp with device and fault modeling.

了解更多 »

Encounter Digital Implementation System

Encounter Digital Implementation System delivers a complete solution for variation- and manufacturing-aware design closure, low power, mixed-signal implementation, and integrated signoff in a single, scalable multi-CPU-enabled design environment for high-capacity, high-performance digital implementation.

了解更多 »