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逻辑设计

Press Releases

Fujitsu Semiconductor Adopts Cadence Chip Planning System for MCU Chips at Its Design Centers Worldwide

Cadence Encounter Digital Flow Instrumental in Tapeout of Samsung 20-Nanometer Test Chip

	IMS CHIPS Standardizes on Cadence Silicon Realization Product Line for Advanced Gate Array Design

Articles

Cadence has design flow for SMIC 40nm process

Heard at DAC: the Question on Everyone’s Mind

	EDA360: My Modest Opinion

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	Design Automation Conference (DAC) 2012 06/03/2012 - San Francisco
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Archived Webinars

New Approach to Logic Design: A Shift in the Paradigm from Design for Test to Design with Test

	New Approach to Logic Design: A Shift in the Paradigm from Design for Test to Design with Test
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Cadence Drives Giga-Gate/Gigahertz Design at 28nm with New Digital End-to End Flow

Cadence Offers Optimized Implementation Methodology for Silicon Realization of New ARM Cortex-A15 MPCore Processor

New White Paper: 3D ICs With TSVs — Design Challenges and Requirements

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