Home > Cadence 中国 > 公司产品 > 定制设计 > Cadence Litho Physical Analyzer

Share

  • Email
  • Social Web
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Cadence Litho Physical Analyzer  


Model-Based Design Manufacturability Checking and Contour Shape Prediction

Cadence Litho Physical Analyzer detects and corrects lithography hotspots based on fast, accurate silicon contour prediction to improve parametric yield and chip performance.

Cadence Litho Physical Analyzer Datasheet »

Product ImageCadence® Litho Physical Analyzer detects manufacturability issues missed by traditional DRC check in a fraction of the time required by solutions based on OPC and lithography simulation. It quickly and accurately accounts for systematic manufacturing variations, helping designers improve yield during physical implementation.

Cadence Litho Physical Analyzer also provides designers with advanced DFM hotspot detection and correction capabilities. Its physics-based modeling technology finds lithography hotspots and enables repair based on fast and accurate silicon contour prediction across the process window. Designers can use these predicted silicon contours for further electrical DFM analysis with Cadence Litho Electrical Analyzer.

Features/Benefits
  • Detects yield-limiting variability hotspots and produces fixing guidelines
  • Checks cells in second, full chips in hours
  • Integrates with current library, IP, custom analog, and cell-based digital physical design flows
  • Delivers fast, silicon-accurate contour shape prediction across the process window
  • Integrates with Cadence Litho Electrical Analyzer for electrical DFM analysis

 
HomeProducts HomeAllegro AMS SimulatorAllegro Design AuthoringAllegro Design Entry Capture / Capture CISAllegro Design PublisherAllegro Design WorkbenchAllegro FPGA System PlannerAllegro Package DesignerAllegro Package SIAllegro PCB DesignerAllegro PCB LibrarianAllegro PCB SIAllegro System ArchitectAssura Physical VerificationCadence 3D Design ViewerCadence ActiveParts PortalCadence AMS Methodology KitCadence Chip OptimizerCadence Chip Planning SystemCadence CMP PredictorCadence Incisive Verification KitCadence InCyte Chip EstimatorCadence Litho Electrical AnalyzerCadence Litho Physical AnalyzerCadence Low-Power Methodology KitCadence MaskCompose Reticle and Wafer Synthesis SuiteCadence OrCAD Capture / Capture CISCadence OrCAD FPGA System PlannerCadence OrCAD PCB DesignerCadence OrCAD Signal ExplorerCadence Palladium Dynamic Power AnalysisCadence Palladium seriesCadence Palladium XP Verification Computing PlatformCadence Physical Verification SystemCadence PSpice A/D and Advanced AnalysisCadence QRC ExtractionCadence QuickView Layout and Manufacturing Data ViewerCadence RF Design Methodology KitCadence RF SiP Methodology KitCadence SiP Co-DesignCadence SiP Digital ArchitectCadence SiP Digital LayoutCadence SiP Digital SICadence SiP LayoutCadence Space-Based RouterCadence SpeedBridge AdaptersCadence VIP CatalogC-to-Silicon CompilerDesign IPEncounter Conformal Constraint DesignerEncounter Conformal ECO DesignerEncounter Conformal Equivalence CheckerEncounter Conformal Low PowerEncounter DFT ArchitectEncounter DiagnosticsEncounter Digital Implementation SystemEncounter Library CharacterizerEncounter Power SystemEncounter RTL CompilerEncounter RTL Compiler Advanced Physical OptionEncounter Timing SystemEncounter True-Time ATPGFirst Encounter Design Exploration and PrototypingIncisive Design Team ManagerIncisive Design Team SimulatorIncisive Desktop ManagerIncisive Enterprise ManagerIncisive Enterprise SimulatorIncisive Enterprise Specman Elite TestbenchIncisive Enterprise VerifierIncisive Formal VerifierIncisive Plan-to-Closure MethodologyIncisive Software ExtensionsIncisive Xtreme seriesNanoRoute RouterOpen Verification MethodologyOrCAD Capture and Capture CISOrCAD PCB Designer OrCAD Signal ExplorerPSpice A/D and Advanced AnalysisRapid Prototyping PlatformSoC Encounter RTL-to-GDSII SystemVirtual System PlatformVirtuoso Accelerated Parallel SimulatorVirtuoso AMS DesignerVirtuoso Analog Design EnvironmentVirtuoso Chip Assembly RouterVirtuoso DFMVirtuoso Digital ImplementationVirtuoso Layout MigrateVirtuoso Layout SuiteVirtuoso Multi-Mode SimulationVirtuoso Passive Component DesignerVirtuoso Power SystemVirtuoso RF DesignerVirtuoso Schematic EditorVirtuoso SiP ArchitectVirtuoso Spectre Circuit SimulatorVirtuoso UltraSim Full-Chip SimulatorVoltageStorm Power Verification

 Content Query Web Part ‭[4]‬