定制设计 

电路设计 对定制IC设计非关键方面进行有选择的自动设计使工程师能够集中精力于设计中的精密工艺部分。Cadence®电路设计解决方案支持快速准确的设计概念输入—包括以自然融入原理图的方式管理设计意图配合先进的设计环境，使工程师能够看到和了解模拟、RF或混合信号设计之间的多种相关性，以及其对电路性能的影响。

Virtuoso Schematic Editor

Provides a complete design and constraint composition environment for front-to-back analog, custom-digital, RF, and mixed-signal designs.

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Virtuoso Analog Design Environment

Provides a comprehensive array of capabilities for electrical and statistical analysis, verification, and optimization of analog/mixed-signal designs, including the interfaces to many industry-standard simulators.

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模块级仿真 对更小模块的处理（重点在准确性和速度）需要模块级的分析。Cadence®模块级仿真技术是一款集成解决方案，该解决方案能够满足设计师不断变化的仿真需求—从架构探索、模块级开发、RF设计直到最终的全芯片验证，实现自动化的测试功能，以便设计者能够快速了解电路是否正常工作。

Virtuoso Multi-Mode Simulation

Enables comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.

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Virtuoso Spectre Circuit Simulator

Delivers a fast, SPICE-accurate simulator for challenging analog, RF, and mixed-signal circuit simulation and device characterization.

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Virtuoso Accelerated Parallel Simulator

Delivers scalable performance and capacity at full Spectre-level accuracy across a broad range of complex analog, RF, and mixed-signal blocks and subsystems.

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芯片级仿真 芯片级仿真将设计中的所有模块视为一个整体，注重性能和准确性。Cadence®芯片级仿真解决方案提供了大容量与高性能，以确保无论模块性能以何种方式来表述，整个芯片均能按原来的设计意图正常工作。

Virtuoso Multi-Mode Simulation

Enables comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.

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Virtuoso Spectre Circuit Simulator

Delivers a fast, SPICE-accurate simulator for challenging analog, RF, and mixed-signal circuit simulation and device characterization.

了解更多 »

Virtuoso Accelerated Parallel Simulator

Delivers scalable performance and capacity at full Spectre-level accuracy across a broad range of complex analog, RF, and mixed-signal blocks and subsystems.

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Virtuoso UltraSim Full-Chip Simulator

Delivers the capacity, accuracy, and speed for transistor-level verification of large custom-analog, digital, mixed-signal, RF, memory, and SoC designs.

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混合信号仿真 目前的片上系统设计将复杂的模拟模块与数字模块集成在一起，需要进行完整的测试与分析才能了解模拟电路与数字电路之间的交互方式，以及互相之间产生的影响。Cadence®混合信号仿真解决方案能够将业界领先的模块级以及全芯片模拟仿真器，与先进的数字分析技术结合在一起。这种卓越的分析方式也支持扩展的多种设计描述语言及RF分析的能力。

Virtuoso Multi-Mode Simulation

Enables comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.

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Virtuoso AMS Designer

Provides an advanced mixed-signal simulation solution for design and verification of analog, RF, memory, and mixed-signal SoCs.

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物理实现 物理实现包括在原理图中进行设计输入，并将其转换为说明芯片实际制造方式的数字蓝图。Cadence®“构造即正确”（Correct-by-Construction）物理实现解决方案能够利用来自代工厂和定制设计者自身经验的设计规则，支持软件以“定制”的方式执行布局布线。

Virtuoso Digital Implementation

Provides a complete synthesis/place-and-route system for small digital block implementation in the context of a schematic-driven, mixed-signal design methodology.

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Virtuoso Layout Suite

Provides the complete physical layout environment of the industry-standard Virtuoso custom design platform, a comprehensive solution for front-to-back custom-analog, digital, RF, and mixed-signal design.

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布线 当设计中的所有元件完成布局后，它们必须通过布线互连，定制IC设计者通常对关键的网段进行手动布线，以减少寄生参数带来的影响。Cadence®布线解决方案采用由设计者制定的手动布线决策，并基于设计规则自动执行其余线网的布线流程。在更小的工艺节点中，这一工作会因为数量巨大而难以进行手动实现。

Virtuoso Layout Suite

Provides the complete physical layout environment of the industry-standard Virtuoso custom design platform, a comprehensive solution for front-to-back custom-analog, digital, RF, and mixed-signal design.

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Virtuoso Chip Assembly Router

Performs automated and interactive block and chip authoring for custom-digital, mixed-signal, and analog designs—at any level of the hierarchy.

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Cadence Space-Based Router

Offers the performance and capacity to handle designs with growing complexity and increasing digital and analog/mixed-signal content.

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寄生参数提取与分析 在布线之后，设计者必须重新回到设计中提取寄生参数，然后执行另一轮的仿真，以分析因为寄生参数影响而导致的问题。用于寄生参数提取和分析的Cadence®解决方案使设计者能够轻松获得设计中所有参数效果的整体概览，然后通过实时标记，指出设计规则中的违规情况，并尽可能迅速地对其进行更正。

Virtuoso Power System

Enables custom design teams to efficiently analyze power and signal integrity for all designs implemented using a custom methodology.

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Virtuoso Analog Design Environment

Provides a comprehensive array of capabilities for electrical and statistical analysis, verification, and optimization of analog/mixed-signal designs, including the interfaces to many industry-standard simulators.

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Cadence QRC Extraction

Performs 3D full-chip parasitic extraction on all design style and flows. Delivers the fastest convergence on design goals.

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芯片完工集成 创建定制IC的最后一个阶段包括通过执行最顶层的布线和电源布线（电源线和时钟树）来完成模拟和数字模块的集成。Cadence®独有的芯片完工集成方法能够将包含各种最佳技术的Encounter®数字IC与Virtuoso®定制IC设计解决方案集中在一起，能够提供更加准确的全芯片实现。

Cadence Physical Verification System

Offers a front-to-back design, implementation, and signoff flow in a single solution. Speeds turnaround of design-rule check and layout vs. schematic verification.

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Cadence Litho Physical Analyzer

Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.

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Cadence Litho Electrical Analyzer

Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.

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Encounter Digital Implementation System

Delivers a complete solution for giga-gate/GHz, low-power, and mixed-signal designs at advanced and mainstream process nodes in a single, scalable multi-CPU–enabled design environment.

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Virtuoso Layout Suite

Provides the complete physical layout environment of the industry-standard Virtuoso custom design platform, a comprehensive solution for front-to-back custom-analog, digital, RF, and mixed-signal design.

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可制造性验证 在今天现金的工艺节点下，定制IC设计软件的考虑更小的晶体管，更细的走线，更密集的布局，更大规模的集成度所带来的挑战。Cadence可制造性解决方案把芯片是如何制造的以及产生掩模板的知识，引入到芯片设计阶段，帮助工程师在芯片流片之前，对制造过程中可能产生的物理效应进行补偿设计，从而提供一种可靠的方法来保证可制造性的验证。

Assura Physical Verification

Performs design-rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.

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Cadence Physical Verification System

Offers a front-to-back design, implementation, and signoff flow in a single solution. Speeds turnaround of design-rule check and layout vs. schematic verification.

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Cadence Chip Optimizer

Uses a 3D space-based approach that models, analyzes, and optimizes layout according to electrical constraints, manufacturing rules, and objectives.

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Cadence Litho Physical Analyzer

Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.

了解更多 »

Cadence Litho Electrical Analyzer

Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.

了解更多 »

Virtuoso DFM

Accurately assess both physical and electrical variability to ensure the manufacturability of custom and mixed-signal designs, libraries, and IP.

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Cadence CMP Predictor

Optimizes design performance through model-based intelligent metal fill and hotspot detection and correction.

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建库 因为在更新的技术中几何继续收缩，所以开发与特定制造工艺相匹配的元件库正变得越来越重要。Cadence®库开发解决方案不仅能使元件开发、库验证和组件技术创建自动化，还能促进IP的重复利用。

Virtuoso Layout Migrate

Offers rapid physical layout migration, including support for complex design rules at advanced nodes.

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Assura Physical Verification

Performs design-rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.

了解更多 »

Cadence Chip Optimizer

Uses a 3D space-based approach that models, analyzes, and optimizes layout according to electrical constraints, manufacturing rules, and objectives.

了解更多 »

Cadence CMP Predictor

Optimizes design performance through model-based intelligent metal fill and hotspot detection and correction.

了解更多 »

Cadence Litho Electrical Analyzer

Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.

了解更多 »

Cadence Litho Physical Analyzer

Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.

了解更多 »

Cadence Physical Verification System

Offers a front-to-back design, implementation, and signoff flow in a single solution. Speeds turnaround of design-rule check and layout vs. schematic verification.

了解更多 »

Cadence QRC Extraction

Performs 3D full-chip parasitic extraction on all design style and flows. Delivers the fastest convergence on design goals.

了解更多 »

Cadence Space-Based Router

Offers the performance and capacity to handle designs with growing complexity and increasing digital and analog/mixed-signal content.

了解更多 »

Encounter Digital Implementation System

Delivers a complete solution for giga-gate/GHz, low-power, and mixed-signal designs at advanced and mainstream process nodes in a single, scalable multi-CPU–enabled design environment.

了解更多 »

Virtuoso Accelerated Parallel Simulator

Delivers scalable performance and capacity at full Spectre-level accuracy across a broad range of complex analog, RF, and mixed-signal blocks and subsystems.

了解更多 »

Virtuoso AMS Designer

Provides an advanced mixed-signal simulation solution for design and verification of analog, RF, memory, and mixed-signal SoCs.

了解更多 »

Virtuoso Analog Design Environment

Provides a comprehensive array of capabilities for electrical and statistical analysis, verification, and optimization of analog/mixed-signal designs, including the interfaces to many industry-standard simulators.

了解更多 »

Virtuoso Chip Assembly Router

Performs automated and interactive block and chip authoring for custom-digital, mixed-signal, and analog designs—at any level of the hierarchy.

了解更多 »

Virtuoso DFM

Accurately assess both physical and electrical variability to ensure the manufacturability of custom and mixed-signal designs, libraries, and IP.

了解更多 »

Virtuoso Digital Implementation

Provides a complete synthesis/place-and-route system for small digital block implementation in the context of a schematic-driven, mixed-signal design methodology.

了解更多 »

Virtuoso Layout Migrate

Offers rapid physical layout migration, including support for complex design rules at advanced nodes.

了解更多 »

Virtuoso Layout Suite

Provides the complete physical layout environment of the industry-standard Virtuoso custom design platform, a comprehensive solution for front-to-back custom-analog, digital, RF, and mixed-signal design.

了解更多 »

Virtuoso Multi-Mode Simulation

Enables comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.

了解更多 »

Virtuoso Power System

Enables custom design teams to efficiently analyze power and signal integrity for all designs implemented using a custom methodology.

了解更多 »

Virtuoso Schematic Editor

Provides a complete design and constraint composition environment for front-to-back analog, custom-digital, RF, and mixed-signal designs.

了解更多 »

Virtuoso Spectre Circuit Simulator

Delivers a fast, SPICE-accurate simulator for challenging analog, RF, and mixed-signal circuit simulation and device characterization.

了解更多 »

Virtuoso UltraSim Full-Chip Simulator

Delivers the capacity, accuracy, and speed for transistor-level verification of large custom-analog, digital, mixed-signal, RF, memory, and SoC designs.

了解更多 »