Chip complexity continues to grow and chip designers are under a lot of pressure to put a lot of software content in their chips. Bluespec helps alleviate some of these pressures with its technologies that support the early use of emulation and FPGA prototyping. George Harper, the company's VP of marketing, explains why a close collaboration with Cadence and the use of Cadence's Rapid Prototyping Platform helped make its hybrid prototyping solutions a success.
Allegro Microsystems has small, custom digital blocks to implement. By hand, such designs were taking up to three days to complete. With the Virtuoso® Custom Placer and Virtuoso Space-based Router in Cadence's Virtuoso Layout Suite, Allegro cut that place-and-route time down to a less than a day and reduced its block size by 30%. Watch the video to hear what Steve Nedeau, senior IC layout engineer, says about how the tools have made his life easier.
Watch this video for insights into Global Unichip's successful tapeout of a 20nm testchip with Cadence and TSMC. Albert Li, marketing director at Global Unichip, talks about the collaborative effort and overcoming advanced node challenges such as double patterning and new design rules.
Automotive parts manufacturer Hyundai MOBIS was facing electromagnetic interference (EMI) problems with its PCB designs. In this short video clip, Imran Shaik, a project lead on EMI simulations, discusses how Cadence® Sigrity™ PowerSI™ and Cadence Sigrity SPEED2000™ helped the company reduce its PCB testing time and get its products to market faster.
At STMicroelectronics, engineers were presented with a design in the C model, yet the register-transfer level (RTL) would not become available for another five to six weeks. The engineers wanted to make use of this time and start their verification process. In this short video, Karl Herterich, senior IC verification engineer at the company, explains how Cadence and its Incisive® Specman Elite® Testbench helped the team adjust its verification environment so it could work on the C model first, then RTL for signoff. STMicroelectronics gained a shorter verification cycle in the process.
At advanced process nodes, new challenges such as layout-dependent effects emerge. STMicroelectronics needed to address these challenges and automate its full custom analog layout flow. Watch this video to hear Preeti Kapoor, a design engineer at the company, talk about using design constraints (specifically, modgens) to create a faster and more accurate DRC clean design.
Dr. Jeroen Fonderie
Taping out 17 different projects over 3 1/2 years seemed like a tall order for Touchstone Semiconductor. But with a helping hand from Cadence Hosted Design Solutions, the startup got its CAD environment set up smoothly and has successfully rolled out 71 high-performance analog ICs since its founding in 2010. Simply put, Hosted Design Solutions lets Touchstone focus on what it does best - designing circuits. Watch this video to hear the company’s VP of engineering, Dr. Jeroen Fonderie, discuss how Cadence helped his company get off the ground.
Expert Engineer at Avago Technologies
Jack Benzel, Expert Engineer at Avago Technologies, describes how the new GigaOpt technology in Encounter Digital Implementation (EDI) System boosts IC design quality.
David Paquet & Julie Sulisthio
Sr. CAD Manager & Sr. CAD Engineer at Micron Technology
Hear from David Paquet, Sr. CAD Manager and Julie Sulisthio, Sr. CAD Engineer from Micron Technology as they talk about the use of Physical Verification System Constraint Validator in conjunction with Virtuoso Constraint System to validate design intent and improve design quality.
Director of Engineering at Applied Micro
Sumbal Rafiq, Director of Engineering at Applied Micro, describes the use of the Cadence Encounter RTL-to-GDSII flow to implement the company’s high performance 2.4GHz X-Gene Server-on-chip embedding the world’s first 64-bit ARM processor.