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06/06/11
Getting a Jumpstart on 20nm - Part I
Distinguished panelists discuss the challenges and approaches that need to be considered when designing and implementing at the 20nm node. Moderated by Jim Handy, the panel includes Philippe Magarshack - STMicroelectronics, Ana Hunter - Samsung, Simon Segars - ARM, and Chi-Ping Hsu - Cadence.
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06/06/11
Getting a Jumpstart on 20nm - Part II
Distinguished panelists discuss the challenges and approaches that need to be considered when designing and implementing at the 20nm node. Moderated by Jim Handy, the panel includes Philippe Magarshack - STMicroelectronics, Ana Hunter - Samsung, Simon Segars - ARM, and Chi-Ping Hsu - Cadence.
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05/11/11
Josh Moore
Cadence
Josh Moore, Senior Product Manager for OrCAD, shares how the new OrCAD Capture Marketplace – with online apps – transforms the way PCB designers access information, discover new resources and extend the OrCAD environment.
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05/03/11
System Development Suite – Narendra Konda, Director Hardware Engineering, NVIDIA
Narendra Konda of NVIDIA outlines how the Cadence System Development Suite helps his design team successfully integrate complex hardware and software, quickly develop app-ready systems, and ultimately improve the overall quality of their products.
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05/03/11
System Development Suite – Nimish Modi, Senior Vice President, System and Software Realization Group, Cadence Design Systems
Nimish Modi of Cadence discusses system development trends, customer challenges, and how the Cadence System Development Suite enables concurrent hardware/software design and verification at every stage of the development cycle.
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05/03/11
System Development Suite – Ran Avinun, Marketing Group Director, Cadence Design Systems
Ran Avinun of Cadence discusses software development and system engineering requirements and Cadence solution including the two new platforms: the Rapid Prototyping Platform and the Virtual System Platform to address alternative limitations.
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05/03/11
Virtual System Platform – Sanjay Srivastava, SoC realization, Cadence Design Systems
Sanjay Srivastava of Cadence discusses firmware challenges and requirements as part of IP delivery and how Cadence Virtual System Platform helped his team to solve these challenges in order to deliver a high quality software and hardware IP to a Cadence customer on time.
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03/23/2011
Hear about 3D-IC/TSV Design Methodology from Cadence R&D
Find out what it takes to handle 3D-IC/TSV design challenges
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02/23/2011
Cadence Opens NASDAQ Stock Market
Lip-Bu Tan, Cadence President and Chief Executive Officer and members of the Executive Management Team rang the opening bell at the NASDAQ stock market on Tuesday morning, February 23, 2011.
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02/23/2010
Cadence Opens NASDAQ Stock Market
Lip-Bu Tan, Cadence President and Chief Executive Officer and members of the Executive Management Team rang the opening bell at the NASDAQ stock market on Tuesday morning, February 23 marking our 5th anniversary of being listed on the NASDAQ exchange.
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02/07/2011
Global Unichip Corporation (GUC) partners with Cadence for giga-gate/GHz, 28nm design
Albert Li, Director of Design and Development at Global Unichip Corporation, outlines the benefits of partnering with Cadence for giga-gate/GHz, 28nm design.
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02/01/2011
Silansys Semiconductor
Niall O hEarcain, the CEO of Silansys Semiconductor describes the benefits of partnering with Cadence for advanced RF level and multimillion-gate designs.
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02/01/2010
New Encounter Digital Implementation System enables superior design productivity and quality
Sumbal Rafiq, Director of Engineering at Applied Micro Circuits, describes the success with the Cadence Encounter Digital Implementation System.
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12/07/2009
Cadence Virtuoso Gets Major Upgrade
Steve Lewis, product marking director for the Cadence Virtuoso technology, discusses the latest productivity, capacity and ease-of-use enhancements to the company’s flagship custom IC and mixed-signal product suite.
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11/10/2009
A Conversation with John Bruggeman, Cadence Chief Marketing Officer
In this video interview, John Bruggeman talks about his previous marketing experience, his role and responsibilities as the new Cadence CMO, as well as the direction ahead for both Cadence and the EDA industry.
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10/19/2009
Cadence-ARM Collaboration
Steve Glaser, corporate vice president of strategy and planning, discusses the collaboration between Cadence and ARM to create a next-generation SoC design flow that accelerates time to market while lowering the cost of SoC integration and verification. The flow provides mutual customers better methods to optimize SoC integration architectures and IP selection, and provides VIP-based automation to speed both performance and functional verification time.
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10/14/2009
Tom Anderson Discusses the Expanded Mmulticore Support for Key Cadence Products
Tom Anderson, product marketing director for enterprise verification, discusses the expanded multicore support for many key Cadence products. Cadence engineers have created parallel algorithms to ensure design teams using multicore machines can reap significant performance benefits.
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10/05/2009
The Incisive Enterprise Verifier
Sarah Lynne Lundell discusses the new Incisive Enterprise Verifier, which delivers the dual power of formal analysis and simulation engines. Sarah discusses some of the product’s unique features—and how they can benefit verification teams deploying them.
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05/18/2009
Cadence and Virtutech Extend Metric-Driven Verification to Virtual System Development
In this video, recorded at CDNLive EMEA 2009, Ran Avinun, Marketing Group Director of System Design and Verification at Cadence, describes the combined offerings of Virtutech Simics and Cadence Incisive software extensions and how it improves quality and project predictability for teams creating and using virtual platforms.
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05/18/2009
Hemant Shah Comments on Cadence Announcement of FPGA-PCB Co-Design Solution
Cadence introduced an innovative FPGA-PCB Co-Design solution at CDNLive EMEA 2009. Hemant Shah, Allegro PCB Products Marketing Director at Cadence, explains what this announcement is about through a very short Q&A session.
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06/19/2008
San Jose Mayor Chuck Reed Honors Cadence Design Systems
San Jose Mayor Chuck Reed honors Cadence on its 20th anniversary by declaring June 19, 2008 Cadence Day.
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06/16/2008
Cadence Corporate Overview
Consumers continue to demand sleeker, faster, thinner, and ever more functional electronic devices. Cadence is proud to lead in providing the innovative software that enables our customers to achieve breakthrough results. Take a look to see more of why we are in the things you can't do without.
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06/1/2008
Cadence among the best in Silicon Valley
Last November, Cadence was included in a list of the 50 Best Places to Work in Silicon Valley by San Jose Magazine. As a result of our placement, on June 1, Cadence was featured on the CBS 5 - KPIX television show, Best Places to Work, along with several other leading Bay Area companies.
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04/28/2008
CDNLive! 2008 EMEA
A successful CDNLive! EMEA recently concluded in Munich, Germany. More than 620 customers representing more than 200 European and international companies attended the event. The event centered on the Cadence product roadmap, EDA techtorials, and Designer Expo, and proved to be a constructive networking platform for discussing the various challenges of electronic design automation. In this podcast we hear customers and guest speakers talking about their experience attending the event and it will give you an excellent view on the EDA industry get-together.
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