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Of the original 250 abstracts submitted and 107 presentations chosen for CDNLive! Silicon Valley 2008, these submissions are being recognized for excellence:

The Best Paper award went to "New Technologies for 6 Gbps Serial Link Design & Simulation, a Case Study," by Donald Telian, Consultant, Paul Larson, Hitachi; Ravinder Ajmani, Hitachi; Kent Dramstad, IBM; and Adge Hawes, IBM.

The steering committee also gave out an honorable mention award and named the People's Choice awards for each of the nine technical tracks (see below).

PAPER AWARDS

• Best Paper - 8ICP88
  New Technologies for 6 Gbps Serial Link Design & Simulation, a Case Study
  Donald Telian - Signal Integrity Consultant
  Paul Larson - Senior Hard Disk Drive Development Engineer, Hitachi GST
  Ravinder Ajmani - Senior Engineer, Hitachi GST
  Kent Dramstad - ASIC Application Engineer, IBM
  Adge Hawes - Development Architect, IBM
• Honorable Mention - Best Paper - 9RF7
  Validation Techniques for Substrate Coupling Analysis
  Glenn Murata - Telegent Systems
  Venkat Ramasubramanian - Cadence Design Systems, Inc.
  Juan Cordovez - Sentinel IC Technologies

PEOPLE'S CHOICE AWARDS

• Track 1 - 1FV8
  Into the Light: Embracing the Open Verification Methodology (OVM)
  Anil Raj Gopalakrishnan - Magnum Semiconductor, Inc.
  Vishal Jain - Cadence Design Systems, Inc.
• Track 2 - 2FV9
  Capturing AMS Coverage with SystemVerilog in Traditional Analog Flow
  Marcelo Silva - SiRF Technology
• Track 3 - 3LD12
  When Do You Know When You've Saved Enough Power?
  David Weir - Cadence Design Systems, Inc.
• Track 4 - 4DI10
  Extending SoC Encounter Using Built-in db Commands
  Jason Gentry - Avago Technologies
• Track 5 - 5OA4
  First Level Checker for IC61 Techfiles for TSMC PDKs
  Robert Makofske - Cadence Design Systems, Inc.
  Steven Chen - TSMC
• Track 6 - 6CR4
  Easy Prototyping in Mixed Signal Custom Design Automated Trial Layout (ATL)
  Dan Clein - PMC-Sierra, Inc.
• Track 7 - 7PD3
  Cadence Allegro PCB Editor (V16.01) - Tips - Did You Know...?
  Vincent Di Lello - Kaleidescape, Inc.
• Track 8 - 8ICP7
  Customizing Constraint Manager with the Advanced Constraints Feature
  Dennis Nagle - Cadence Design Systems, Inc.
• Track 9 - 9RF7
  Validation Techniques for Substrate Coupling Analysis in Advanced RF/Analog
  Glenn Murata - Telegent Systems
  Venkat Ramasubramanian - Cadence Design Systems, Inc.
  Juan Cordovez - Sentinel IC Technologies