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Tuesday    |    Wednesday
Conference Agenda - Wednesday March 14   

9:00am-9:50am  
Track 1
Digital		 Track 2
Mixed Signal/ Low Power		 Track 3
Custom		 Track 4
Verification		 Track 5
PCB		 Track 6
System/ Software/
IC Packaging		 Track 7
System Verification		 Track 8
Special Topics
DIG202
Comprehensive QRC/ETS solutions for 28nm Timing Signoff
Texas Instruments India		 MSL201
Conformal Low Power - Complex Low Power Design Verification
Qualcomm Inc.		 CUS010
AMS Reference Flows for Advanced TSMC CMOS Processes
TSMC 		SIV102
Formal Verification of a QoS-based Arbiter
Marvell Semiconductor		 PCB101
A Comprehensive Analysis and Verification Methodology for DDR3 Interfaces
EMA Design Automation 		SYS201
Reference Flow for Early Software Development and Verification with ARM-based TLM Virtual Prototypes Including Connection to RTL
TSMC		 SYV008
Challenges and solutions for implementing SoC designs in multi-FPGA prototyping systems
Cadence 		DIG105
Mitigating Power Delivery Risk with Cadence Early Rail Analysis
Integra Design Solutions

10:00am-10:50am
DIG001
Encounter Digital Implementation Floorplan Route Planning using Bus Guides
Avago Technologies 		MSL202
Low Power Implementation on Freescale Kinetis Family
Freescale		 CUS005
From 6 Days to 6 Minutes: Accelerating Mixed-Signal Design Verification of a 45nm 2.4GHz Sigma-Delta Fractional-N Frequency Synthesizer Using Virtuoso AMS Designer Empowered by Automated Behavioral Modeling
Orora Design Technologies Inc.		 SIV103
Mechanism to allow easy writing of test cases in a SystemVerilog Verification environment, then auto-expand coverage of the test case
Verifysys LLC		 PCB102
Accelerating the Methodology of PCB PDN Design and Analysis
Cadence		 SYS006
Leveraging Virtual Platforms in Compute Sub-System Design
ARM		 SYV104
At-Speed Waveform Generation for Test Pattern Using Cadence Palladium
Freescale Semiconductor		 DIG106
Hierarchical Synthesis Flow
Cadence

11:00am-11:50am
DIG004
28nm digital methodology for dynamic RAM logic
Rambus 		MSL006
Low-Power Format CPF in Analog and Mixed-Signal Simulation and Macro IP Verification
Cadence 		CUS102
A User-Oriented SKILL Based Tool for Pre-Extraction Power-Grid Optimization, Targeting Accurate IR-Drop Analog Transient Simulations
SPANSION		 SIV005
Metric-Driven Verification: Going the Extra Mile
IBM 		PCB001
PCB and package co-design using 3D EM full wave simulation
CST		 SYS005
Rapid IP-centric Virtual Prototype Development
Duolog		 SYV004
Verifying Cache Coherent Designs, ACE and Interconnect Monitor
Cadence		 DIG107
Parasitic Extraction Challenges for Display Technologies and its Applications
IGNIS

Noon - 1:30pm LUNCH / R&D  

1:30pm-2:20pm  
DIG203
Cadence EDI System Interface and Implementation with IBM ASIC
Cisco/IBM		 MSL007
SPEF/DSPF Parasitic Stitching in Post-Layout Analog and Mixed-Signal Simulation
Cadence 		  SIV201
Module Testing vs. Full Chip Verification - Methodology and Practical Tips
Veriest Venture		 PCB002
Why Doesn't My Board Work?
Adiva Corporation		 SYS103
Fast Processor Models for SystemC Virtual Platforms
Imperas		 SYV005
No spin zone: Solid State Drives rock storage interfaces
Cadence		 DIG005
Automated Strategy Selection in Conformal LEC for Easy Verification Closure
Cadence/ OmniVision

2:30pm-3:20pm  
DIG108
Distributed Parallel Test Architecture
Netronome Systems Inc.		 MSL002
An Efficient Phase-Locked Loop Noise Simulation Using APS & ViVA
NVIDIA 		CUS007
An Evaluation of Fluid Guard Rings
Freescale Semiconductor 		SIV104
UVM SDMAM technique for System Level SOC verification
Freescale Semiconductor		 PCB003
IPC2581—The 21st Century Approach to Transferring Design Data to Manufacturing
Fujitsu Network Communications/ Cadence 		PKG001
Multi chip Module (MCM) package design flow using Cadence SiP design tools and Agilent package analysis
Analog Devices Inc. 		SYV201
System-C to Layout Metal-Only Engineering Change Orders: Fantasy or Reality?
Cadence		 MSL004
High Performance, Interoperable Real Number Models for Mixed-Signal Verification
SI Labs

3:20pm-3:45pm BREAK  

3:45pm-4:35pm  
DIG103
Electrical Variability due to Layout Dependent Effects: Analysis, Quantification, and Mitigation on 40 and 28nm SOC Designs
CSR 		MSL003
Verilog-AMS Verification of ADC Soft IP cores
Missing Link Electronics 		CUS008
Minimizing Schematic Migration with Autonomous Super Symbols
Freescale Semiconductor		 SIV006
Techtorial: Low Power Failures – What not to Plan
Cadence		 PCB103
Creating Apps for OrCAD Capture: Experiences, Tips, and Examples
EMA Design Automation 		PKG002
Using Co-Design to Optimize System Interconnect Paths
Broadcom & Cadence		 SYS102
Efficient enterprise deployment of verification computing platforms solving diverse verification
Texas Instruments		 MSL203
Substrate Noise Analysis and Wide Metal Extraction for Power MOS embedded LSIs
Renesas

4:45pm-5:35pm  
DIG104
RC Bottom-up DFT insertion in a hierarchical Place-and-Route flow
Imagination Technologies		 MSL107
Use-model schemes for AMS OSS/IRUN flow with multiple digital abstractions
Texas Instruments Inc.		 CUS202
PVS Double Patterning Technology for 20nm
Cadence		 SIV007
Low-power Verification using UVM SystemVerilog
Cadence		 PCB004
Improving IDF geometry definitions
Teradyne, Inc.		 PKG101
Silicon-Package-Board Co-Design and Co-Analysis for a High Performance Multicore Chip
Bayside Design Inc.		 SYV007
Why DisplayPort will be the next display choice of PC Vendors, OEMs and their verification challenges
Cadence		  

Related link:
- Additional Allegro/OrCAD roadmap/techtorial content

NOTE: Agenda is subject to change.