Home > CDNLive > Silicon Valley > 2012 > Agenda - Tuesday March 13th

Tuesday    |    Wednesday
Conference Agenda - Tuesday March 13   

9:00am - 9:50am
Track 1
Digital 		Track 2
Mixed Signal/ Low Power		 Track 3
Custom		 Track 4
Verification		 Track 5
SoC/DIP		 Track 6
System/ Software		 Track 7
System Verification		 Track 8
High
Performance
DIG003
In-Design DFM in Digital Implementation: Process Hotspot Repair at the 32/28nm Node Using Pattern Matching
Samsung Electronics 		MSL101
A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP
Rambus Inc. 		CUS201
GLOBALFOUNDRIES 28nm Analog & Mixed Signal Production Ready Flow
GLOBALFOUNDRIES/ Cadence 		SIV101
A Methodology for Concurrent Coverage-Driven Verification
Freescale Semiconductor 		SOC001
Integrating 28nm DDR PHYs – Challenges and Considerations
Cadence		 SYS001
SDS/System: General Presentation Overview
Cadence		 SYV001
SDS/System: General Presentation Overview
Cadence		 HPA001
Flow and library validation on a 22nm SOI testchip
ARM

10:00am - 10:30am BREAK  

10:30am - Noon
KEYNOTE SPEAKERS
Lip-Bu Tan
President and Chief Executive Officer, Cadence Design Systems
Rick Cassidy
President, TSMC North America
Tom Lantzsch
Executive Vice President of Corporate Development, ARM
  

Noon - 1:30pm LUNCH / EXPO  

1:30pm - 2:20pm  
DIG101
Quantifying the design impact of Double Patterning for the 20nm and 14nm technology nodes
IBM 		MSL001
IC 61 and EDI 10.1 Inter-Operability Flow, Features and Benefits
Maxim Integrated Products 		CUS001
LDE Aware Design Flow Automation
Freescale Semiconductor 		SIV001
Best Practice of Assertion-Based Verification
LSI 		SOC004
3D Stacking of DRAM: Why Wide-IO is driving TSV
Cadence 		SYS002
Easing the Concurrent Hardware and Software Development with Standards, Tools and Virtual Platforms
Xilinx 		SYV101
Functional Verification of Next Generation ICs with Next Generation Tools – Applying Palladium XP Simulation Acceleration to an Existing Specman Testbench Framework
PMC-Sierra 		HPA101
Being Green – what Good design and ccopt (formerly Azuro) can do to reduce Power
Netronome Systems Inc.

2:30pm - 3:20pm  
DIG102
Early Architecture Exploration using EDI
Cisco 		  CUS101
20nm technology challenges on PDK development
STMicroelectronics 		SIV002
Bypassing Bypass Logic Verification Trouble with Automation of Memory Wrapper Verification (Without UVM, VMM, or OVM)
Cisco 		SOC003
Deployment of Advanced PCI Express Gen3 Controller IP in Networking and Storage Applications
Marvell 		SYS003
Virtual Platforms: technology, application and experiences
ARM 		SYV105
Enabling a new paradigm of system-level debug productivity while maintaining full in circuit emulation performance
AMD		 HPA002
Mali-T604 Embedded General Purpose Computing for GPU implementation in CMOS32LP using Cadence Reference Methodology
ARM

3:20pm - 3:45pm BREAK  

3:45pm - 4:35pm  
DIG201
Parasitic Extraction with QRC at 20nm
GLOBALFOUNDRIES		 MSL103
RNM Model Development and Application in Mixed-Signal SOC Verification
LSI Corporation 		CUS002
Circuit Prospector as a design reuse and modification tool
ADI 		SIV003
Customized Metric Driven Verification Planning and Management
LSI Corporation 		SOC101
Optimization of graphics data flow between Vivante's high performance GPUs and Cadence's DDR controller IP
Vivante Corporation 		SYS004
Enterprise Configuration and Change Management of EDA ,Systems and Embedded Software assets with IBM Rational ClearCase & ClearQuest
IBM 		SYV102
Verification IP: growing from IP focus to full System design, system verification and testing
Cadence 		HPA102
Implementation strategies for a high performance and low-power ARM® Cortex™-A15 processor: Methodology and tools usage best practices
Texas Instruments

4:45pm - 5:35pm  
DIG002
How Conformal Constraint Designer enhanced our design flow
APM (Applied Micro) 		MSL104
AMS Simulation of full duplex USB interface using strength modeled Connect Modules
Texas Instruments Inc. 		CUS003
Bring sign-off quality verification earlier in design flow with Virtuoso Integrated Physical Verification System
Cortina Systems		 SIV004
Design and Testbench Analysis: The SystemVerilog Challenge
Cadence		 SOC201
PCIe post silicon validation
LeCroy 		SYS101
200X acceleration of HW/SW integration and debug using a virtual A15 CPU sub-system and emulated RTL
Cadence		 SYV003
SysML addressing EDA needs with IBM Rational Rhapsody
IBM		 HPA103
Improving Performance, Power and Area of a High Speed Dual-core ARM Cortex-A9 Processor with Clock Concurrent Optimization Technology
Broadcom

5:45pm - 7:30pm PARTNER RECEPTION / EXPO  

NOTE: Agenda is subject to change.