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Home > CDNLive > Silicon Valley > 2010 > Call for Papers

Overview
Realizing EDA360 – Call for Papers October 26, 2010 — Fairmont Hotel, San Jose CA

The Call for Papers is now closed!

If you have submitted an abstract, you will be notified of your status no later than September 17. First draft of presentations will be due October 6.

Guidelines for preparing your abstract

  • Prepare your abstract for a 25-minute session, not counting audience Q&A.
  • Set up the problem/need your session will address. (1-2 sentences)
  • How will your session solve this problem/meet this need? Mention the main points/topics your session will cover. (1-3 sentences)
  • What technologies, services, or methodologies were employed to meet this need? (1-2 sentences)
  • What case study(ies) will be cited as examples of success? (1-2 sentences)
  • How will your session help attendees or their customers? Will they save time to market? Reduce overhead? Increase productivity? Quantify the big benefit. Example: saved 6-8 weeks. (1-2 sentences)
  • 1500 character limit (including spaces)

Content tips

Rating of abstracts for final papers and presentations will be based upon the following criteria:

  • Clarity – Well organized and easily understood. A good indicator of what can be expected in the full-length paper.
  • Relevance – Of interest to the user group audience and in line with the track topic.
  • Technical impact – Important results, techniques, or case studies of special significance.
  • Originality – New design methodologies employed or a case study for an innovative design.
  • Practicality – Reference products in a case study or as a proof-of-concept for a design methodology, but avoid product pitches. The goal is to demonstrate feasibility or illustrate a concept, not sell the product.


 
Suggested Hot Topics:

Mixed-Signal Design
- Design and verification
- Implementation
- Packaging and SiP

Optimizing Designs for Low Power

IP Quality and Qualification
- SoC and IP integration challenges and methodologies
- Memory and I/O subsystem design
- IP reuse methodologies
- IP performance optimization

System-Level Design and Verification
- Hardware-assisted verification
- TLM-driven design and verification
- System Realization for ARM-based devices

Verification
- Verification methodologies – UVM
- Multi-language UVM
- Debug
- Multi-core simulation
- Metric-driven verification
- Mixing simulation and formal verification

Front-End Design
- Evolving from RTL-to-GDSII to TLM-to-GDSII
- TLM-to-GDSII ECO solutions
- Planning and pre-RTL exploration
- Predictable test methods
- Validating integration-ready IP

Digital Implementation
- High-performance ARM-core based design
- Ultra–large-scale (25M+ instance) design
- 3D (stacked die) IC design with TSV
- Advanced 20nm design and double-patterning

Digital Signoff
- Leveraging signoff analysis in your design flow
- Low-power design and signoff
- Chip-package-board co-design

Full Custom and Analog Design
- Solving critical issues in analog design
- Solving mixed-signal design (analog/custom on top) issues
- Critical issues and challenges in RF design
- Leveraging SKILL to solve design challenges

PCB Design
- FPGA-PCB co-design
- PCB signal and power integrity
- Library and design data management

IC Packaging and SiP Design
- Signal and power integrity
- 3D IC integration with silicon interposers and stacked die
- Chip-package-board co-design

Design for Manufacturing
- "Correct-by-design" manufacturability and variability-aware implementation
- In-design DFM signoff: addressing mixed-signal and SoC designs with Virtuoso and Encounter
- DRC+: automated litho-unfriendly pattern matching and fixing in Virtuoso and Encounter
- Prevention, analysis, optimization, and signoff