|
Mixed-Signal Design
- Design and verification
- Implementation
- Packaging and SiP
Optimizing Designs for Low Power
IP Quality and Qualification
- SoC and IP integration challenges and methodologies
- Memory and I/O subsystem design
- IP reuse methodologies
- IP performance optimization
System-Level Design and Verification
- Hardware-assisted verification
- TLM-driven design and verification
- System Realization for ARM-based devices
Verification
- Verification methodologies – UVM
- Multi-language UVM
- Debug
- Multi-core simulation
- Metric-driven verification
- Mixing simulation and formal verification
Front-End Design
- Evolving from RTL-to-GDSII to TLM-to-GDSII
- TLM-to-GDSII ECO solutions
- Planning and pre-RTL exploration
- Predictable test methods
- Validating integration-ready IP
Digital Implementation
- High-performance ARM-core based design
- Ultra–large-scale (25M+ instance) design
- 3D (stacked die) IC design with TSV
- Advanced 20nm design and double-patterning
Digital Signoff
- Leveraging signoff analysis in your design flow
- Low-power design and signoff
- Chip-package-board co-design
Full Custom and Analog Design
- Solving critical issues in analog design
- Solving mixed-signal design (analog/custom on top) issues
- Critical issues and challenges in RF design
- Leveraging SKILL to solve design challenges
PCB Design
- FPGA-PCB co-design
- PCB signal and power integrity
- Library and design data management
IC Packaging and SiP Design
- Signal and power integrity
- 3D IC integration with silicon interposers and stacked die
- Chip-package-board co-design
Design for Manufacturing
- "Correct-by-design" manufacturability and variability-aware implementation
- In-design DFM signoff: addressing mixed-signal and SoC designs with Virtuoso and Encounter
- DRC+: automated litho-unfriendly pattern matching and fixing in Virtuoso and Encounter
- Prevention, analysis, optimization, and signoff
|