Cadence CDNLive! Silicon Valley 2010 Agenda

Conference Agenda

8:00am	BREAKFAST

9:00am - 9:15am	Welcome Lip-Bu Tan, President and CEO, Cadence

9:15am - 9:45am	Cadence Product Strategy John Bruggeman, Senior Vice President and Chief Marketing Officer, Cadence

9:45am - 10:15am	Cadence Silicon Realization Chi Ping Hsu, Ph.D, Senior Vice President, Research and Development, Silicon Realization, Cadence Dave Desharnais, Product Marketing Group Director, Silicon Realization, Cadence

10:15am - 10:30am	Break

10:30am - 11:00am	Customer Perspective: Texas Instruments Raul A. “Ty” Garibay, Jr., Director of OMAP IC Engineering, Wireless Terminals Business Unit

11:00am - 11:40pm	EDA360 In the Real World Panel Moderator: Vishal Kapoor, Vice President, Product Management, New Businesses Vice President, Strategic Business Alliances, Cadence Panelists include ARM, Common Platform, GLOBALFOUNDRIES, and Open Silicon

11:40am - 11:50am	Wrap-up

11:50pm - 1:15pm	Lunch

1:35pm - 2:20pm

System Realization	SoC Realization	Silicon Realization	Silicon Realization	Silicon Realization	Silicon Realization
[Advanced] Transaction-Based Acceleration: Strong Ammunition in any Verification Arsenal Varun Gupta, Cadence	[General] Innovative Power Management Techniques for Advanced SoC Design Frank Ferro, Sonics, Inc.	[General] Functional Integration-Level Verification Strategy Using Incisive Software Extensions, AMS, Specman, and Incisive Enterprise Manager Joel Artmann, Medtronic (FV)	[Intermediate] Leveraging the Cadence OA ITDB to Create Process-Option-Based PDKs Asif Khan, Texas Instruments (MS)	[General] IC 6.1 Foundry Methodology to Release PDKs (Analog) with Standard Digital Libraries Ofer Tamir, Towerjazz (CIC)	[General] Less Pessimism by Applying Design-Specific OCV Analysis Michio Komoda, Renesas (LP)

2:25pm - 3:10pm

[Advanced]
Metric-Driven Verification Using TLMs
Per Edstrom and Ajay Goyal, Cadence

[Intermediate]
Resolving the IP-SoC Tower of Babel
Kurt Wolf, Silicon-IP, Inc.
Vikram Phatak, Silicon Enablers
Kenneth Wang, Silicon-IP, Inc.

[General]
Tips and Pitfalls for the First-Time OVM User
Dan Steinberg, Google
Dorit Kerem, Cadence

[Intermediate]
B0 in A1: Implementing Metal-Stepping Mega ECOs and the Associated Risks/Rewards
Robert Dwyer, Cadence
Ranjit LoboPrabhu, Netronome Systems Inc.

(IMP)

[Advanced]
Simulating PLL Jitter and Phase Noise Using Transient Noise Analysis
Bob Mullen, Cadence
Philip Chen, TSMC

(CIC)

3:10pm - 3:25pm

15 MIN BREAK

3:25pm - 4:10pm

[Intermediate]
Mixed-Signal Simulation Experience with Multi-Chip Module Design
Sundaram Sangameswaran, Texas Instruments

(MS)

[Intermediate]
Pcell Generation with the Cadence PAS Tool
Romain Feuillette, ST Microelectronics

(CIC)

4:15pm - 5:00pm

[Intermediate]
TLM2 Modeling for OVM-Based Functional Verification
Kevin Locker, System Silicon LLC

[Advanced]
OVM-Based Verification of Analog IP and Mixed-Signal SoCs
Hao Fang, LSI
Neyaz Khan, Cadence

[Intermediate]
Improving Verification Productivity with Verification Environment Reuse
Gurudutt Bansal and Swapnajit Chakraborti, Cadence

(FV)

[Intermediate]
SKILL Rejuvenated: Extending SKILL Language Syntax
Sylwester Warecki, Freescale

5:05pm - 5:50pm

5:55pm - 6:40pm

[Intermediate]
Real Portable Models for System/ Verilog/ A/ AMS
Bill Ellersick, Analog Circuit Works

(MS/VERIF)

[Intermediate]
Analog Layout Automation: A Transition to 6.1.x at TI
Donna Duchame, Texas Instruments

(CIC)

6:45pm - 9:00pm

NOTE: Agenda is subject to change.