Home > CDNLive > Silicon Valley > 2009 > Agenda

Week 1 (Oct 5 - Oct 9)    |    Week 2 (Oct 12 - Oct 16)
CDNLive! Silicon Valley 2009 Webinar Series Choose from more than 60 technical webinars, grouped by design domain!

Week 1 webinars are available to attend either online or onsite at Cadence Headquarters in San Jose, where you can also mingle with other Cadence customers and Cadence staff during the breaks. Complimentary lunch will be provided to all attendees in San Jose.

Registration for week 2 is now closed.
Attend onsite in San Jose
October 5-9
and October 12-13
Cadence Headquarters
2655 Seely Avenue, Building 10
San Jose, CA 95134
Map

Attend online
October 5-9
and October 12-16
Attendee instructions provided with registration

 WEEK 1: October 5-9

  Monday, October 5
Track 1 - Custom IC
9:00am - 10:15am PST An Efficient Noise-Aware Flow Simulating a 2.4GHz Fractional-N PLL Frequency Synthesizer with AMS Designer
Junjie Yang & Robert A. Mullen - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
10:30am -11:45am PST Mixed-Signal Verification using IRUN with OSSNetlister
Natarajan Krishnan - Cadence Design Systems
Sundaram Sangameswaran - Texas Instruments
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 2:15pm PST Reliability Simulation in the Virtuoso Analog Design Environment
Xiao Wang, Alvin Chen, Tina Najibi, Tianlei Guo, Xuehua Fu - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
2:30pm - 3:45pm PST Mixed-Signal Verification using VHDL-SPICE
Diwakar Ramamurthy and Andre Baguenier - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
Track 2 - Custom IC
9:00am - 10:15am PST Runams: A simple command line way to run AMS Designer in ADE
Tina Najibi, Xiao Wang, Vijay Seti, Ruilin Yue - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
10:30am - 11:45am PST Full Chip Transistor-Level EMIR Analysis & Visualization with DSPF stitching using Ultrasim
Rajeshekhar Chimmalagi - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 5:00pm PST Verification of Multi-band Digitally-controlled RFIC Using Virtuoso MMSIM
Hany El Hak - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
Track 3 - PCB Design
9:00am - 10:15am PST Using OrCAD Capture to Drive Constraints within an Allegro PCB Editor High-Speed Flow
David Price - DFM
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
Track 4 - IC Packaging & SiP
10:30am - 11:45am PST Enabling IC-Package Co-design for a Distributed Team Environment
Thomas Whipple - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 2:15pm PST Power Distribution Network (PDN) Simulation for Complex Flip Chip Packages
Suresh Subramaniam - Tabula
Bala Vishwanath, Swagato Chakraborty, Dipanjan Gope, Vikram Jandhyala - Physware
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.

  Tuesday, October 6
Track 1 - Custom IC
9:00am - 10:15am PST A conventional model playback utility in the Cadence design environment
Kristin Nan Liu - National Semiconductor
Ken Hung - National Semiconductor
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
10:30am -11:45am PST Fully customizable routing flow in Virtuoso using the Routing Design Environment
Farrukh Zafar & Steve Riley - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 2:45pm PST Introduction to Virtuoso 6.1 Workshop
Alessandra Costa - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
3:00pm - 5:00pm PST Introduction to Virtuoso 6.1 Workshop
Alessandra Costa - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
Track 2 - Custom IC/RF Design
9:00am - 10:15am PST Phase-Noise Simulation and Measurement for VCOs with Bandgap Voltage Reference
Yu Zhu, Helene Thibiero, Andrew Li - Cadence Design Systems
Ted Blank, Nand Jha - Texas Instruments
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
10:30am - 11:45am PST Scalable, Reusable and High Performance Mixed-signal Verification using AMSD Incisive Use Model (AIUM)
Chandrashekar Chetput, Pranav Bhushan, Abhi Kolpekwar, Junjie Yang and Natarajan Krishnan - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 2:45pm PST Using design constraints in Virtuoso 6.1 Workshop
Brian La Borde - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
3:00pm - 5:00pm PST Using design constraints in Virtuoso 6.1 Workshop
Brian La Borde - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.

  Wednesday, October 7
Track 1 - Logic Design
9:00am - 10:15am PST Architectural SOC Prototyping with Power Intent Considerations
An IDT Case Study by
Kenneth Chang/Camille Kokozaki
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
10:30am -11:45am PST Automating ECO's on Complex Designs
Kenneth Chang - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 2:15pm PST Concurrent Low Power and Multi-Mode optimization Synthesis Flow using the Common Power Format (CPF) flow
Laszlo Borbely - Micron
Shankar Vellanthurai & Tiffany Hsiao - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
Track 2 - System Design & Verification
9:00am - 10:15am PST SystemC TLM Design and Verification Solution Overview
Robert Juliano - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
10:30am - 11:45am PST ARM Fast Models and Incisive SystemC TLM2 Interoperability
Barry Spotts - ARM
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 2:15pm PST CoWare and Cadence SystemC TLM Based Co-Verification Solution
Patrick Sheridan - CoWare
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
2:30pm - 3:45pm PST Virtutech and Incisive Software Extensions Integration
David Beal - Virtutech
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
Track 3 - System Design & Verification
1:00pm - 4:00pm PST SystemC TLM Design and Verification Workshop
Leonard Druker & Robert Juliano - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.

  Thursday, October 8
Track 1 - Functional Verification
9:00am - 9:30am PST Incisive Platform Software Update
Tom Anderson - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
9:30am - 10:15am PST Combining Simulation and Formal Analysis for Memory Controller Verification
Ying Yu - Marvell
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
10:30am -11:45am PST Time-Saving Formal Analysis Approach for Multiple IP Connectivity Verification
Chaitanya Kosaraju - Xilinx
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 2:15pm PST Quantifying the Value of Formal Analysis for Verifying a Memory Expander Chip
Yogesh Bhagwat - Cisco
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.

  Friday, October 9
Track 1 - Digital Implementation
9:00am - 10:15am PST Applying DRCPlus in the Router: Automatic Elimination of Lithography Hotspots using 2D Pattern Detection and Correction
Jie Yang - AMD
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
9:00am - 10:15am PST System Validation of the Cortex - A9 Multicore Processor
Bryan Dickman - ARM Ltd
Online Webinar registration - Now closed.
10:30am -11:45am PST Variation-Aware Design Flow for 45nm and below using Electrical DFM
Nishath Verghese - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 2:15pm PST Implementing a complete Low Power Flow from Architecture to GDSII
Bambuda Leung - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
Track 2 - Functional Verification
9:00am - 1:00pm PST Introduction to Metric Driven Verification
John Nehls - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
Track 3 - Digital Implementation
9:00am - 10:30am PST Using an Integrated Signoff Power, Timing, SI and Extraction Flow to Drive Faster Design Convergence
Stephan Mahnke - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
10:45am - 12:15pm PST Increasing mixed-signal physical implementation productivity using Virtuoso and Encounter
Marie Kunesh - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
Track 4 - PCB Design
9:00am - 10:15am PST Don't let Automation make You Lose Sight of your Goal
Gregory Horlick - Cadence Design Systems
Alabama
Online Webinar registration - Now closed.
10:30am - 11:45am PST Reducing design cycle times for complex PCB designs through a new methodology - A Corporate Perspective
Masahiro Isono - Hitachi
Online Webinar registration - Now closed.
1:00pm - 2:15pm PST Integrating Global Route Technology into the PCB Design Flow
Sky Huang - ASUS/Pegatron
Online Webinar registration - Now closed.

 WEEK 2: October 12-16

  Monday, October 12
Track 1 - Custom IC
9:00am - 10:15am PST Full Chip Transistor Level Simulation Using Advanced Analog Modeling techniques
Roopak Suri - Freescale Semiconductor
Noida, India
Online Webinar registration - Now closed.
10:30am -11:45am PST Custom Mixed Signal Validation and Verification using IRUN
Steve Jones, Texas Instruments
Diwakar Ramamurthy - Cadence Design Systems
Dallas, Texas
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 2:15pm PST SKILL++ in action “ an alternative implementation of class for C++ programmers.
Sylwester Warecki - Freescale Semiconductor
Arizona
Online Webinar registration - Now closed.
Track 2 - Digital Implementation
9:00am - 10:15am PST Fast, Easy, Early IR Drop Analysis Using Encounter Power System's Early Rail Analysis
Aman Jain - LSI
Pune, India
Online Webinar registration - Now closed.
10:30am - 11:45am PST Construction of a Multiple Mode DDR ASIC Interface using Advanced Techniques of Cadence Encounter
Rob Bassett - Avago Technologies
Fort Collins, CO
Online Webinar registration - Now closed.
1:00pm - 2:15pm PST Variability Analysis of a Standard Cell Library in a 28nm Technology Using Early DFM Models
Kayvan Sadra - Texas Instruments
Dallas, TX
Online Webinar registration - Now closed.
Track 3 - Digital Implementation
10:45am - 12:15pm PST Accelerate Your Advanced Node Design
Rahul Deokar - Cadence Design Systems
Online Webinar registration - Now closed.

  Tuesday, October 13
Track 1 - Functional Verification
9:00am - 10:15am PST Open Verification Methodology with ABV
Sharon Rosenberg - Cadence Design Systems
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
10:30am -11:45am PST Using Abstraction to Extend Formal Analysis to Data-Path Management
Balekudru Krishna & Anamaya Sullery - Chelsio Communications
Online Webinar registration - Now closed.
Onsite attendance -
Walk-ins welcome.
1:00pm - 5:00pm PST OVM Advanced Applications
Brett Lammers, Chris Komar, John Decker - Cadence Design Systems
Online Webinar registration - Now closed.
Track 2 - Custom IC
9:00am - 10:15am PST Design of High Speed CMOS Comparator & High Speed and Low Power Converter for an I/O Buffer
Lokesh Bhaskar - RF Silicon
Noida, India
Online Webinar registration - Now closed.
10:30am -11:45am PST Automated Migration Methodology for Design Database
Victer Chong - National Semiconductor
Malacca, Malaysia
Online Webinar registration - Now closed.
1:00pm - 2:15pm PST Detection and Management of Device Breakdowns for Chip Level Simulation
Aaron Symko - LSI Logic
Mendota Heights, MN
Online Webinar registration - Now closed.
Track 3 - Manufacturability Signoff and High-level Synthesis
9:00am - 10:15am PST PBTI, do designers need to concern?
Tianlei Gou - Cadence Design Systems
Beijing, China
Online Webinar registration - Now closed.
10:30am - 11:45am PST Hierarchical and Connectivity-based Manufacturability Analysis
Mark Levy - IBM
Burlington, Vermont
Online Webinar registration - Now closed.
1:00pm - 2:15pm PST High Level Synthesis of TI QueueManager IP using Cadence C-to-Silicon Compiler, a case study
Maneesh Soni - Texas Instruments
Online Webinar registration - Now closed.

  Wednesday, October 14
Track 1 - Custom IC
9:00am - 10:15am PST nanolib: Library of nanoscale Devices
Gaurav Gandhi, Sudip Sarkar, David Varghese
Cadence Design Systems
Noida, India
Online Webinar registration - Now closed.
1:00pm - 2:15pm PST High Performance Transient Noise Analysis for Asynchronous, Time Sampled or Large Signal Analog and RF Circuits
Helene Thibieroz - Cadence Design Systems
Austin, Texas
Online Webinar registration - Now closed.
Track 2 - Functional Verification
9:00am - 10:15am PST Verification of Advanced Dynamic Power Management in Low Power SoC
Neyaz Khan - Cadence Design Systems
Dallas, TX
Online Webinar registration - Now closed.
10:30am - 11:45pm PST Single Verification IP for design IP developers and design IP integrator
Durlov Khan - Cadence Design Systems
Chelmsford, MA
Online Webinar registration - Now closed.
1:00pm - 2:15pm PST Verification Performance: Where is my Go Faster Button?
Adam Sherer - Cadence Design Systems
Chelmsford, MA
Online Webinar registration - Now closed.
Track 3 - Other
9:00am - 10:15am PST An automated and efficient approach for Quality Assurance of design kit
Dayanand Singh - National Semiconductor
Bangalore, India
Online Webinar registration - Now closed.
10:30am - 11:45am PST Errors with Capacitor EDA Models due to Oversimplification, Temperature, and DC Bias
John Prymak - KMET Electronics
Simpsonsonville, SC
Online Webinar registration - Now closed.
Track 4 - PCB Design
9:00am - 10:15am PST How to efficiently manage and build distributed complex team design using Allegro System Architect
John Hutton - HP ESL R&D
Fort Collins, CO
Online Webinar registration - Now closed.
10:30am - 11:45am PST Using Allegro AMS Simulator to determine VRM parameters for Power Integrity Analysis
Andrew Haas - Cadence Design Systems
Bowling Green, OH
Online Webinar registration - Now closed.

  Thursday, October 15
Track 1 - Custom IC
9:00am - 10:15am PST Checkpoint Methodology for Mixed-Signal Simulation Through Virtuoso ADE
Subash Yadav - Cadence Design Systems
Noida, India
Online Webinar registration - Now closed.
Track 2 - Functional Verification
9:00am - 10:15am PST OOP Falls Short of Verification Needs
Matan Vax - Cadence Design Systems
Israel
Online Webinar registration - Now closed.
10:30am - 11:45am PST Finding the Flow
James Keithan - Design Flow Consultant
Chelmsford, MA
Online Webinar registration - Now closed.
1:00pm - 2:15pm PST Barriers to Wide Scale Acceptance of Assertion Based Verification
Howard Martin - Zocalo-Tech
Austin, TX
Online Webinar registration - Now closed.
2:30pm - 3:45pm PST Project planning for Metric Driven Verification
Paul Carzola - Cadence Design Systems
Dallas, TX
Online Webinar registration - Now closed.
Track 3 - Logic Design
10:30am - 11:45am PST Using SystemVerilog for RTL Design - The Benefits and the Pitfalls
Mark Wight - Galazar
Online Webinar registration - Now closed.
1:00pm - 2:15am PST Routability analysis and physical prediction flow
Nandini Chintala, Harish Ananthamurthy - Cadence Design Systems
Austin, TX
Online Webinar registration - Now closed.

  Friday, October 16
Track 1 - System Design & Verification
9:00am - 10:15am PST IBM Electronics Verification Management Solution - Driving Toward's First Time Right Designs
Alex Baran - IBM
Philadelphia, PA
Online Webinar registration - Now closed.
10:30am -11:45am PST HW/SW Co-Verification Experiences Developing a Next Generation Internet Platform Using Incisive Software Extensions (ISX)
Mohsin Riaz - PMC Sierra
Jason Andrews - Cadence Design Systems
Online Webinar registration - Now closed.
1:00pm - 2:15pm PST Using of Incisive Software Extensions (ISX) and a SystemC TLM2 Virtual Platform to Verify Linux Device Drivers
Jason Andrews - Cadence Design Systems
Central Region
Online Webinar registration - Now closed.
Track 2 - PCB Design
9:00am - 10:15am PST Creating a Custom Constraint in the Constraint Manager to Verify Broadside Differential Pair Routing
David Palumbo - Cadence Design Systems
Lake Katrine, NY
Online Webinar registration - Now closed.
10:30am - 11:45am PST Cadence Allegro Editor (V16.02-V16.2) "Allegro Tips" Did You Know
Vincent Di Lello - Kaleidescape
Canada
Online Webinar registration - Now closed.