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CDNLive! India 2009 — Call for Papers

CDNLive! India conference is seeking abstracts for presentation sessions.

Presentation Sessions

We are soliciting submissions for abstracts for presentations that deal with design tools, design methods and design techniques in a number of categories described below.

Design Tools presentations describe contributions to internal research and development of design tools and their use in your company.

Design Methods and case studies presentations describe innovative methodologies for the design of electronic circuits and systems, as well as creative experiences with design automation in state-of-the-art design projects.

Design Techniques presentations describe the use of design tools and methods from the perspective of a specific design project. They include a brief description of the design and discussion of methodology, flow and innovative use of tools.

LAST DATE FOR SUBMISSION OF ABSTRACTS: Friday July 31, 2009

Abstracts must be a maximum of 500 words, clearly stating the significant contribution, impact, and results of the submission. All abstracts will be reviewed by an external Expert Committee. Authors of accepted presentations must sign a copyright release form for their paper.

Notice of acceptance will be sent via email by Monday, September 21, 2009.

Important Dates

TASK DATE
Call for Papers Open Wednesday, June 3, 2009
Call for Papers Closed Friday, July 31, 2009
Speakers Notified Monday, September 21, 2009
Final Papers/Presentations Due Friday, October 23, 2009
CDNLive! India Paper Review Committee

Abstracts will be reviewed by and Expert Committee that consists of selected Cadence customers and internal experts.

Please note that rating of abstracts will be based upon — and should also include information regarding — the following criteria for the final paper and presentation:

  • Quality – The abstract should be well organized and easily understood. The abstract and summary are good indicators of what can be expected of the prospective authors for a full-length paper.
  • Relevance – The abstract should be highly relevant to the interests of a user group audience, and the track topic in particular.
  • Impact – Submissions reporting on important results, methodologies or case studies of special significance should be considered favourably.
  • Originality – New design methodology or a case study for an innovative design has great educational value.
  • Commercial content – It is acceptable to use a product in a design case study or as a proof of concept for a design methodology, and many of the abstracts a user group views most favourably do just that. However, we also know that the audience responds most negatively to anything that comes across as a product pitch. A good case study that uses a real product in an appropriate manner to demonstrate feasibility or illustrate a concept should be considered favourably.
IMPORTANT GENERAL GUIDELINES FOR BOTH PRESENTATION AND TECHTORIAL SUBMISSIONS
  • Please download the CDNLive! India 2009 Abstract Submission Form to submit an abstract.
  • Abstracts must be submitted in Word or PDF format only.
  • Word limit is 500 words (about 2 pages). Diagrams may be included.
  • Maximum of 4 authors per submission.
  • Email your completed Abstract Submission Form to CDNLive! India

Your abstract should cover:

  • Set up the problem/need your session will address.
  • How will your session solve this problem/meet this need? Mention the main points/topics your session will cover.
  • What technologies, services, methodologies were employed to meet this need?
  • What case study(ies) will be cited as examples of success?
  • How will your session help attendees or their customers? Will they save time to market? Reduce overhead? Increase productivity? What is the Big Benefit? Cite specific quantification. Example: saved 6-8 weeks.

Download Abstract Submission Form »

Questions?
Email CDNLive! India.


 
Suggested Topics:

Functional verification
Transaction-based verification, modeling & acceleration
Hardware/software co-verification - ISX
Verification planning and management
Testbench development and automation
Assertion-based Verification
Formal Analysis
Simulation debug and analysis
Analog-mixed signal system verification
Silicon debug in-circuit emulation
Platform VIP Reuse
Electronic System Level design
Hardware Assisted Verification

Digital IC design
RTL synthesis
Formal verification
Low-power design/estimation in front end
Low power design implementation and analysis
Design for test/yield/manufacturing (DFT, DFY & DFM)
Constraints management and timing analysis
Hierarchical layout, prototyping, and planning
Physical optimization, routing and timing closure
Dealing with ECOs
Coping with variation during implementation
Signoff (timing, power and SI)
Physical verification (DRC, LVS, EM)
New technologies challenges
IP design and reuse
High-performance design

Custom IC design
Analog/RF parasitic extraction and simulation
High-frequency challenges and solutions
Statistical simulation
Circuit optimization
Full custom or mixed-signal floorplanning
Physical automation/ optimization
Physical verification
Voltage drop/electromigration
Mixed-model/mixed-signal simulation and analysis
Test for analog/mixed-signal designs
IC 6.x Adoption
Deep submicron challenges/solutions
Modeling/characterization
Analog/Mixed signal methodology enhancement
RF Design methodology enhancement
IP migration
Substrate extraction and noise analysis
Litho checks at 45nm and below
Library variability analysis
Constraint driven front to back design flow
Custom routing

Silicon-Package-Board
Design partitioning and reuse
Interactive and automatic routing
Design for manufacturing and testability
Signal and power integrity analysis
Simulation model development
Multi-gigahertz design
Design process and automation
Designing in DDR2 memories
Reliability modeling
Design for test/manufacturing and RET signal integrity
Design reuse strategies
Impact of standards on design optimization

Special Interest
OpenAccess
Reliability modeling
Design for test/manufacturing and RET signal integrity
Design reuse strategies
Impact of standards on design optimization