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Call for Papers – Suggested Topics Listed below are suggested Call for Papers topics for CDNLive EMEA 2014.

Custom/Analog and RFTop
• Advanced and high-performance noise analysis for switching circuits
• Analog/mixed-signal design
• Behavioral modeling
• Chip-level integration and routing
• Circuit optimization
• Configuration management
• Constraint-driven design and design/IP reuse
• Dealing with parasitics – design and verification
• Deep submicron challenges and solutions
• Full custom floorplanning
• IC 6.1.5 adoption, best practices, and customer experiences
• In-design DFM
• Interoperability using OpenAccess
• High-performance, post-layout verification methodology
• Layout-dependant effects
• Mixed-mode/mixed-signal simulation and analysis
• Modeling and characterization
• New Virtuoso Space-Based Router and best practices
• PDK migration to IC 6.1 OpenAccess
• PDK automation and test
• Physical automation and optimization
• Physical verification
• Reliability
• RF and high-frequency design challenges
• Statistical simulation
• Thermal considerations
• Tool interoperability and standards
• Verification planning
• Voltage drop/electromigration

Design IPTop
• Non-volatile memory/Flash
• Connectivity: PCI Express, Ethernet, USB
• SerDes/PHY/MAC

Digital (RTL-to-GDSII)Top
• Advanced clocking strategies for managing power and variability
• Advanced node (32nm, 28nm, 20nm, 16nm/14nm) SoC implementation
• Advanced techniques for block implementation and design closure
• Application of statistical methodologies in the design flow
• Clock domain crossing checks
• Complex design planning and floorplanning
• Dealing with pre-mask ECOs
• Design for test, MBIST, LBIST, power-aware test, ATPG, diagnostics
• Flip-chip design and implementation
• Floorplanning, power, placement, CTS, optimization, routing, and associated ECOs
• Formal verification
• High-performance design
• In-design DFM
• IP assembly for SoC design
• Library characterization and modeling requirements for leading-edge design
• Lithography and CMP considerations
• Logical to physical design hierarchy strategies
• Low-power design implementation and analysis (MSV, PSO, biasing, CPF)
• Low-power exploration/design/estimation in the front end
• Managing functional clock complexity
• Managing ECOs from RTL through physical implementation
• Managing hierarchical design
• Managing the interdependencies of electrical signoff
• Mixed-signal design implementation and analysis (A/d, D/a, A/D)
• Model-based vs. rule-based design implementation and analysis
• Modeling physical effects in logic synthesis
• Multi-mode/multi-corner analysis and optimization techniques
• New technology challenges
• Parasitic extraction
• Physical verification
• Post-mask ECOs using spare gates
• Power Integrity and Signoff
• RTL synthesis
• SiP considerations
• Through-silicon via (TSV) and stacked-die design and implementation
• Timing and manufacturing variability analysis
• Timing constraint strategies and analysis
• Timing signoff
• Verification of timing constraints
• Verification of integration-ready IP

Functional VerificationTop
• Analog/mixed-signal SoC verification
• Assertion-based verification/formal analysis
• Debug and analysis
• High performance SoC, IP/subsystem, and gate-level simulation
• Low-power functional verification and modeling
• Metric-driven verification
• Mixed formal and simulation methodologies and applications
• SoC verification
• Specman-testbench automation
• SystemVerilog/UVM testbench automation and extensions
• Verification planning and management

IC Packaging, SiP, and PCB DesignTop
• Chip-package-board system prototyping
• Chip-package-board system signal and power analysis
• Constraint-driven design
• Constraint-driven design for power integrity
• Design automation and tool customization
• Designing in DDR3/DDR4 memories
• Design partitioning and reuse
• Design for manufacturing and testability
• ECAD/MCAD/thermal integration
• EMI reduction techniques
• FPGA/PCB integration
• Front-end design capture
• High-density interconnect (HDI) and flex designs
• Library and data management
• Integration with PLM systems
• Interactive and automatic routing
• Multi-gigabit design
• Package-on-package design techniques and challenges
• Schematic-less design entry
• Signal and power integrity analysis
• Silicon/package co-design
• Simulation model development

Low PowerTop
• Low-power design methodologies and flows
• Low-power and ultra-low-power design techniques
• Power estimation methodologies and flows

Mixed SignalTop
• Analog/mixed-signal behavioral modeling
• Analog, mixed-signal, and RF design methodologies and flows
• Analog, mixed-signal, and RF simulation
• Low-power verification of mixed-signal designs
• Metric-driven verification for analog/mixed-signal design
• OA-based interoperability flow between Virtuoso and Encounter

Special TopicsTop
• Design for test and manufacturing
• DFY/DFM optimization techniques and results
• Reliability modeling
• Working with foundries
• Yield optimization (linking design and fab)

System Design and VerificationTop
• Embedded software development and verification
• FPGA-based prototyping
• Hardware/software integration and verification
• High-level synthesis/TLM design and verification methodologies
• In-circuit emulation, simulation acceleration, and synthesizable testbench
• Performance analysis
• Software-driven verification
• System design, integration, and emulation
• Verification IP

Should you have any questions about abstract submissions, please email marketing_euro@cadence.com.

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