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Home > CDNLive > EMEA > 2013 > Suggested Topics

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Call for Papers – Suggested Topics Listed below are suggested Call for Papers topics for CDNLive EMEA 2013.

Low-PowerTop
• Low-power design, verification and implementation methodologies and flows
• Low-power design techniques or design techniques and flows for ultra power savings
• Power estimation methodologies and flows
• Dynamic Power analysis

Mixed-SignalTop
• Miixed-signal behavioral modeling
• Mixed-signal design methodologies and flows
• Mixed Signal verification methodologies and flows
• Mixed Signal Physical Implementation methodologies and flows
• Metric driven verification for analog and mixed-signal design
• Interoperability using OpenAccess

Custom/Analog /RF Design and ImplementationTop
• Advanced and high-performance noise analysis for switching circuits
• Analog design
• Behavioral modeling
• Chip level integration and routing
• Circuit optimization
• Configuration management
• Constraint-driven design and design/IP reuse
• Full custom floorplanning
• Deep submicron challenges and solutions
• Full custom floorplanning
• IC 6.1.5 adoption, best practices, and customer experiences
• Interoperability using OpenAccess
• High-performance, post-layout verification methodology
• Layout dependant effects
• Mixed-mode simulation and analysis
• Modeling and characterization
• New Virtuoso Space-Based Router and best practices
• PDK migration to IC 6.1 OpenAccess
• PDK automation and test
• Physical automation and optimization
• Physical verification
• Reliability
• RF and high-frequency design challenges
• Statistical simulation
• Deep submicron challenges and solutions
• Thermal considerations
• Tool interoperability and standards
• Verification planning

Digital Design and ImplementationTop
• Advanced clocking strategies for managing power and variability
• Advanced node (32nm, 28nm, 20nm) SoC implementation
• Advanced techniques for block implementation and design closure
• Clock domain crossing checks
• Complex design planning and floorplanning
• Dealing with pre-mask ECOs
• Design for test/ATPG
• Flip-chip design and implementation
• Floorplanning, power, placement, CTS, optimization, routing, and associated ECOs
• Formal verification
• High-performance design
• Logical to physical design hierarchy strategies
• Low-power design implementation and analysis (MSV, PSO, biasing, CPF)
• Low-power exploration/design/estimation in the front end
• Managing functional clock complexity
• Managing ECOs from RTL through physical implementation
• Managing hierarchical design
• Managing the interdependencies of electrical signoff
• Mixed-signal design implementation and analysis (A/d, D/a, A/D)
• Model-based vs. rule-based design implementation and analysis
• Multi-mode/multi-corner analysis and optimization techniques
• New technology challenges
• Post-mask ECOs using spare gates
• RTL synthesis
• Modeling physical effects in logic synthesis
• SiP considerations
• Through silicon via (TSV) and stacked-die design and implementation
• Timing and manufacturing variability implementation
• Timing constraint strategies

Functional VerificationTop
• Assertion-based verification/formal analysis
• Debug and analysis
• Low-Power functional verification
• Metric-driven verification
• UVM and Metric Driven Design for Mixed Signal
• Mixed formal and simulation methodologies and applications
• SoC verification
• Specman-testbench automation
• SystemVerilog/UVM testbench automation and extensions
• Verification planning and management
• Verification IP

System Design and VerificationTop
• Embedded software development and verification
• Virtual Platforms
• FPGA-based prototyping
• Hardware/software integration and verification
• High-level synthesis
• TLM design and verification methodologies
• In-circuit emulation, simulation acceleration and synthesizable testbench
• Software-driven verification
• HW/SW co-verification and debug
• Verification IP
• System design, integration and emulation

Silicon SignoffTop
• DRC, ERC and LVS
• Static Timing Analysis
• Signal Integrity
• Dealing with parasitics – design and verification
• Voltage drop/electromigration
• Design for manufacturing
• DFY/DFM optimization techniques and results
• Reliability modeling
• Working with foundries
• Yield optimization (linking design and fab)
• Lithography and CMP considerations
• Library characterization and modeling requirements for leading-edge design

IP/VIPTop
• Cadence Verification IP use and reuse
• Use of Cadence IP
     •  DDR
     •  NVM Express
     •  Nand Flash
     •  PCI Express
     •  Ethernet/Automotive Ethernet
• IP assembly for SoC design

IC packaging, SiP design, and PCB designTop
• Chip-Package-Board System Prototyping
• Chip-Package-Board System Signal and Power Analysis
• Constraint-driven design
• Design automation and tool customization
• Designing in DDR3/DDR4 memories
• Design partitioning and reuse
• Design for manufacturing and testability
• ECAD/MCAD/thermal integration
• EMI reduction design techniques
• FPGA/PCB integration
• Front-end design capture
• High-density interconnect (HDI) and flex designs
• Library and data management
• Integration with PLM systems
• Interactive and automatic routing
• Multi-gigabit design
• Package-on-package design techniques and challenges
• Schematic-less design entry
• Signal and power integrity analysis
• Silicon/package co-design
• Simulation model development

Academic TrackTop
The topics of interest include (but are not limited to):
• Outstanding industry and university collaborations
• Outstanding courses, laboratories and design projects development
• New concepts in teaching
• Outstanding curricula in Micro- Nanoelectronics education
• Education for entrepreneurship in microelectronics
• Emerging fields in design and technology
• Microelectronics teaching in the future
• Long distance and continuous microelectronics education
• Educational infrastructure: design and IP libraries, CAD tool access

Should you have any questions about abstract submissions, please email cdnlive_emea@cadence.com