Home > CDNLive > EMEA > 2012 > Agenda - Wednesday 16th May 2012

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Wednesday 16th May 2012   

7:30 - 8:30 Welcome Coffee  

8:30 - 9:00    
Silicon Realization
Custom Design		 Silicon Realization
Functional Verification		 Silicon Realization
Digital Implementation		 System Realization
PCB Design & IC Packaging		 System Realization
Design & Verification

 Silicon Realization
Logic Design
 Academic Track
CD07
Technology Overview 		FV07
Using Property Checking to find a difficult bug in DMA block: Industrial Experience
STMicroelectronics		 DI07
Flow and library validation on a 22nm SOI testchip - The Greenseed project
Arm Holdings		 SPB07
PCB and Package Co-design and Co-optimization using Simplified Workflow from Cadence SiP to CST STUDIO SUITE 2012
CST		 SDV01
Technology Overview		 LD01
DfT Architecture and ATPG for JEDEC Wide-IO Memory-on-Logic 2.5D/3D-Stacks
Imec		 AC07
Early Power Estimation in a Mixed-Signal Environment using UVM and RTL Compiler
TUL DMCS & IMMS

9:00 - 9:30    
CD08
Technology Overview		 FV08
Formal Verification of Static Properties in Clock Gating Modules
Freescale Semiconductor		 DI08
Multi voltage domain, multi VT low power physical implementation by using Cadence tool suite
Texas Instruments		 SPB08
More Advances in Creepage and Air Gap Analysis in Electromechanical Products with NEXTRA
Mecadron		 SDV02
Technology Overview 		LD02
Security-Aware Design and Verification Techniques with RTL Compiler
NXP		 AC08
Family of Mulitchannel ASICs for Measurements Electrical Activity of Neural Networks
AGH Univ. of Science and Technology

9:30 - 10:00    
CD09
Technology Overview		 FV09
Fast & complete formal verification of a complex data preprocessor using out-of-the-box Cadence scoreboard properties
Texas Instruments		 DI09
Power Calculation From early estimation to silicon correlation
Renesas Electronics		 SPB09
Analog and Mixed Signal Die to Package checks
Freescale Semiconductor		 SDV03
SyMX -- Model Crossover between Simics and SystemC/TLM Virtual System Platforms
Cadence 		LD03
Early, functional unit based, power estimation for wireless baseband processors
Imec		 AC09
Circuit optimization procedure combines OrCad and Matlab
Technical University of Cluj-Napoca

10:00 - 10:30 Coffee Break  

10:30 - 11:00    
Silicon Realization
Custom Design		 Silicon Realization
Functional Verification		 Silicon Realization
Digital Implementation		 System Realization
PCB Design & IC Packaging		 System Realization
Design & Verification

 Silicon Realization
Logic Design
 Academic Track
CD10
Altis Multi Process PDK Development Platform for fast Creation and QA of Design-Ready IC 6.1.5 PDKs
Altis Semiconductor		 FV10
A UVM-based verification methodology for RFID enabled smart sensor systems
IMMS		 DI10
Implementation of a flexible, low power and high performance 4G baseband processor with the Cadence CPF flow
Imec		 SPB10
Constraint managed, Team-based deisgn methology with Design Re-use
Cadence		 SDV04
The ease of use of Cadence® Virtual System Platform for virtual prototype creation and embedded software development on ARM® fast models and using Verum® ASD:Suite.
Methods2Business 		LD04
Technology Overview		 Special Session - Outstanding Projects

10:30 - 10:45
AC10A
An example of co-operation between two members of the Cadence Academic Network
Technical University of Cluj-Napoca

10:45 - 11:00
AC10B
EDADB Tools: Schematic Porting, Initial Sizing and Advanced Documentation of Circuit Schematics

11:00 - 11:30    
CD11
Area-Based Design Rule Aware Error Correction
Cadence		 FV11
Advanced Verification Techniques for the Mixed-Signal Domain
Duolog Technologies		 DI11
Design Driven By DFM
Arm Holdings		 SPB11
Constraint managed, Team-based deisgn methology with Design Re-use
Cadence		 SDV05
Leveraging Virtual Platforms in Compute Sub-System Design
Cadence 		LD05
Technology Overview		 AC11
A receiver - TDC chip set for accurate pulsed time-of-flight lase ranging
University of Oulu

11:30 - 12:00    
CD12
Analog BIST generation within the Cadence Design Flow
ATEEDA		 FV12
Metric-Driven Verification Flow for AMS IPs
STMicroelectronics		 DI12
Multi Level Partitioning Flow for Giga Scale Designs
Renesas Electronics		 SPB12
Board-to-board co-design - multiple board mechanical solution
Cadence		 SDV06
Sequences: Formalizing software programming sequences to enhance HW/SW integration
Duolog Technologies		 LD06
Technology Overview		 AC12
Model-based Design Space Exploration and Synthesis Flow for Digital Signal Processing Algorithms
Politecnico Di Torino

12:00 - 12:30    
CD13
Verilog-AMS Verification of ADC Soft IP cores
Missing Link Electronics		 FV13
Method of On-the-fly chip verification
IBM		 DI13
Hierarchical cpf usage in ST-HED low power flow
STMicroelectronics		 SPB13
Interconnect Floor Planning - plan, check, commit approach for board connectivity
Cadence		 SDV07
Virtual Platforms: technology, application and experiences
Arm Holdings		 LD07
Looking for uninitialized Flip-Flops with Conformal Constraint Designer (CCD)
NXP		 AC13
SystemC based Model Refinement Flow for System Verification of a GNSS Receiver Frontend
IAS

12:30 - 13:00    
CD14
Customer Acceptance Test Program accelerates adoption of new IC releases for ST’s PDKs
ST & Cadence		 FV14
Auto-generated UVM framework for fast and reusable verification
Dialog Semiconductor		 DI14
Accurate Clock Tree Prototyping for Gigascale Designs
Renesas Electronics		 SPB14
Chip-PCB Co-Simulation with Extracted PCB Net Models
Cadence & Texas Instruments 		SDV08
HW/SW co-verification of a microcontroller debug system
TI 		LD08
Automated Modular ECO Flow :- A Solution for doing Chip Revisions as ECO
University of Logano		 AC14
Steering committee
Cadence Academic Network

13:00 - 14:30 Lunch and Best Paper Presentation in Designer Expo  

NOTE: Agenda is subject to change.