CDNLive! EMEA 2010
4-6 May 2010 Munich, Germany
Hilton Munich Park
CDNLive! EMEA,May 4-6 in Munich, brought together some 430 Cadence® technology users, developers, and industry experts to share ideas, educate and network with each other.
Customers from over 130 European and international companies spent two and a half days participating in user presentations, Cadence demos and techtorials and visiting partners in the EDA ecosystem at the Designer Expo.
Tuesday 4th May 2010
The conference opened its doors at midday on Tuesday 4th May with six techtorials taking place during the afternoon covering:
- Part 1: Virtuoso Custom Design Platform IC 6.1.4 – Best Practices to Constraint-Driven Design
- Part 2: Virtuoso Custom Design Platform IC 6.1.4 – Cascaded Simulations
- Part 3: Physical Verification System - High Performance
- Part 1: IEV (Incisive Enterprise Verifier) – Formal Contributions to Verification Closure
- Part 2: Advanced OVM Applications
System Design & Verification
- Part 1: TLM-driven design and verification; model refinement for high-level synthesis
- Part 2: System Level Low Power Design
- Overcome Design Challenges on your Large, Complex Nanometer Designs
- Part 1: Addressing Routing Congestion during Logic Synthesis
- Part 2: Cost-Aware Design through Accurate Area, Power, Performance and Economic Estimations PCB & IC Packaging
- Part 1: HDI design
- Part 2: DDR3 design & simulation
During the breaks and evening networking event, attendees had the opportunity to visit the Designer Expo and meet with Cadence partners across the electronics industry.
Wednesday 5th May 2010
John Bruggeman, Cadence CMO, commenced the second day with a keynote, launching the EDA360 vision to the EMEA audience and the inviting Vishal Kapoor, VP Marketing, Cadence to present the Cadence Open Integration Platform. Vishal was followed by Subramani Kengeri from GLOBALFOUNDRIES who talked about, “The Need for a Trusted Collaborative Design Ecosystem”.
Dr Alberto Sangiovanni-Vincentelli then gave the Industry Keynote, talking about how the design of complex systems is essentially about “Connections”: Connection of concepts, Connection of objects, Connection of teams.
The rest of the morning and early afternoon consisted of a multitude of customer and Cadence presentations in six Technical Tracks on Custom Design, Digital Implementation, Functional Verification, System Design & Verification, PCB & IC Packaging and an Academic Track was also running. Executive and press attendees attended the Executive Track and the Press Track respectively.
During the afternoon, demonstrations of the latest Cadence products, flows, and methodologies were shown in each of the tracks, with an additional Logic Design track and Cadence Training Language and Methodology Hands-on Sessions.
Wednesday concluded with an event to support the “Go Beyond your Imagination” theme, with Germany’s premier Mind Reader, Thorsten Havener, taking members of the audience and delving into their imaginations!
Thursday 6th May 2010
On the last day of the conference more customer presentations were held in the six technical tracks (including Logic Design) and the academic track. The PCB & IC Packaging track held hands-on workshops.
The best paper for each track, as voted by the conference attendees, was awarded a prize by Wolfgang Stronski, Field Marketing Director EMEA.
CDNLIVE! EMEA 2010 — BEST PAPER AWARDS
Attendees at the CDNLive! EMEA 2010 event took part in voting for the best papers in each major category. We are pleased to announce the winners for each of the following tracks:
- Custom Design Track: Gunar Lorenz, Coventor
MEMS+IC design of a DLP mirror array
- Functional Verification Track: Michael Zwerg, Texas Instruments
Power aware simulation on a mixed-signal SoC with embedded memories
- System Design: Christian Sauer, Cadence
Developing synthesizable IP modules from TLM 2.0 descriptions – A methodology case study
- Digital Implementation Track: Joint Winners
Lyes Djama, STMicroelectronics
Significantly improve Mixed-Signal IC design convergence and Time-to-Market with a new interoperable design solution
Martin Spohr, Renesas Electronics Europe
Plan to Success – Fast Big Chip Hierarchical Floorplan
- Logic Design: Jay Karekar, KPIT Infosystems
Low power techniques for DFT using Cadence DFT tools
- PCB and IC packaging: Ole Ejlersen, Nordcad
Constraint driven design using OrCAD® PCB design tools
- Academic: Dominic Maurath, Albert-Ludwigs-University –Freiburg
Lead institution for AMS Methodology: Mixed-signal design flow and prototype design of ultra-low power energy harvesting power processing modules
2009 Conference Highlights
Highlights | '09 Proceedings
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