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System Design
TLM drive Design and Verification
High Level Synthesis (C, C++, System C)
Power aware system design
System Planning and Management
Functional and System Verification
Power-aware functional verification and modelling
Hardware/software co-verification
Verification planning and management
Specman-testbench automation
Assertion-based verification/formal analysis
Debug and analysis
Analog/mixed-signal system verification
Verification IP use and reuse
In-circuit emulation/transaction-based acceleration
SoC verification
SystemVerilog/OVM testbench automation
Metric Driven verification
Low Power verification
Logic Design
Modeling physical effects in logic synthesis
Managing functional clock complexity
Logical to physical design hierarchy strategies
RTL synthesis
Formal verification
Low-power exploration/design/estimation in the front end
Design for test/ATPG
Timing constraint strategies and analysis
Dealing with pre-mask and post-mask ECOs
New technology challenges
IP assembly for SoC design
High-performance design
What is broken in logic design?
Chip planning
Digital Implementation
Low-power design implementation and analysis (MSV, PSO, biasing, CPF)
Mixed-signal design implementation and analysis (A/d, D/a, A/D)
What changes for designs at 65/45nm technology nodes?
Managing hierarchical design
Hierarchical layout, chip assembly, prototyping, partitioning/budgeting, padring optimization, and associated ECOs
Complex design planning and floorplanning
Advanced techniques for block implementation and design closure
Floorplanning, power, placement, CTS, optimisation, routing, and associated ECOs
Timing and manufacturing variability implementation and analysis (statistical analysis, DFM-aware)
Model-based vs. rule-based design implementation and analysis
Lithography and CMP considerations
Application of statistical methodologies in the design flow (timing, leakage, analysis, optimisation)
Multi-mode/multi-corner analysis and optimisation techniques
Managing the interdependencies of electrical signoff (timing, power and signal integrity, DFM-aware)
Through silicon via (TSV) and stacked-die design and implementation
Flip-chip design and implementation
Library characterisation and modeling requirements for leading-edge design
SiP considerations
Advanced clocking strategies for managing power and variability
Managing ECOs from RTL through physical implementation
Physical Verification
Custom IC Design and RF Design
Constraint-driven design and design/IP reuse
RF and high-frequency design challenges
Physical automation and optimisation
New Virtuoso Space-Based Router and best practices
Full custom floorplanning
Physical verification
Reliability
Voltage drop/electromigration
Thermal considerations
Analog/mixed-signal design
Behavioural modeling
Mixed-mode, mixed-signal simulation and analysis
Dealing with parasitics – design and verification
IC 6.1.3 adoption, best practices, and customer experiences
Modeling and characterisation
Statistical simulation
Circuit optimisation
Verification planning
Deep submicron challenges and solutions
IC packaging, SiP design, and PCB design
Front-end design capture
Schematic-less design entry
Constraint-driven design
Design partitioning and reuse
Library and data management
Integration with PLM systems
Interactive and automatic routing
Design for manufacturing and testability
Signal and power integrity analysis
Simulation model development
Multi-gigahertz design
Design automation and tool customisation
Designing in DDR memories
Silicon/package co-design
Package-on-package design techniques and challenges
High density interconnect (HDI) and flex designs
ECAD/MCAD/thermal integration
FPGA/PCB integration
EMI reduction design techniques
SiP and board I/O planning and design
Manufacturability Signoff
Working with foundries
Reliability modelling
Design for test and manufacturing
Signal integrity
Yield optimisation (linking design and fab)
DFY/DFM optimisation techniques and results
Physical Verification
Special Topics
Interoperability using OpenAccess
Process design kit migration to IC 6.1 OpenAccess
Process design kit automation and test
Configuration management
Tool interoperability and standards
Chip-level integration and routing
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