Conference Agenda : Wednesday, May 20
| 8:45 - 9:15 |
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Custom Design
Track |
Digital Implementation
Track |
Functional Verification
Track |
System Design and Verification Track |
Silicon-Package Board
Track |
Academic
Track |
CD07
Techniques to reduce Simulation Time
IBM
|
DI07
Implementing CortexA9 Multicore Processors for High performance and Low Power Requirements at 65nm and below using ARM-Cadence iRM
Arm Holdings
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FV06
Moving from direct testing to Metric driven verification by utilizing verification IPs: A Case study
Ericsson
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SD&V01
System Design and Verification Roadmap
|
SPB06
Design Constraints for PCB with Gbit Serial Links
FlowCAD
|
AC07
Experience with the FSMDesigner4 high level design entry tool for design and verification in research and teaching
University of Heidelberg, Germany
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| 9:15 - 9:45 |
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CD08
Constraints, Constraint Groups and the Incremental Technology Database
Cadence Design Systems
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DI08
Migration towards a CPF-integrated and automated low-power physical implementation flow on design derivatives
Silicon & Software Systems
|
FV07
Can a single Verification IP meet both design IP developers and design IP integrators requirements? Test studies from actual engagements.
Cadence Design Systems
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Continue
System Design and Verification Roadmap
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SPB07
Using redundancy in electronic systems to improve system reliability
BQR Reliability Engineering Ltd
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AC08
InCyte ChipEstimator in Research and Education
University of Paderborn, Germany |
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| 9:45 - 10:15 |
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CD09
Custom Design Roadmap
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DI09
Developing and optimizing ultra-low power microcontrollers
Cadence Design Systems
|
FV08
Integration of a PCI Express UVC in an existing OVM based environment
Univ of Heidelberg
|
SD&V02
Architectural analysis at transaction level with C++ TxE
STMicroelectronics & Cadence Design Systems
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SPB08
MOCHA, Modelling and CHAracterization for SiP – Signal and Power Integrity Analysis
Cadence Design Systems
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AC09
Cadence Academic Network at AGH UST: education, science and cooperation with industry
AGH University Krakow, Poland |
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| 10:15 - 10:45 |
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Continue
Custom Design Roadmap
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DI10
Low Skew - Low Power CTS Methodology in SOC-Encounter for ARM Processor Cores
Arm Holdings
|
FV09
Don't Ass-U-Me Your Formal Assumptions - Use Verification Planning
Cadence Design Systems
|
SD&V03
Reduced verification effort using software/hardware coverification
El Camino
|
SPB09
A Language for Description and Verification of SiP Layout Design Rules
Cadence Design Systems
|
AC10
Analysis of Voltage Dithering in High Level Synthesis
Universität Tuebingen, Germany |
|
| 10:45 - 11:15 |
Coffee Break |
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| 11:15 - 11:45 |
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CD10
A MIXED-SIGNAL/MEMS CMOS Co-Design Flow with MEMS-IP Publishing/Integration
Cadence Design Systems
|
DI11
Digital Implementation Roadmap
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FV10
Advanced e and SystemVerilog Programming
AMIQ Consulting
|
SD&V04
System Validation of the Cortex-A9 Multi Processor
Arm Holdings
|
SPB10
Global Chip-Package Methodology for Physical and Electrical Co-design of Re-Distribution-Layers (RDLs).
NXP
|
AC11
Virtual teaching using CAD tools for the design and applications of micro-nanoelectronic systems
Institute of Microelectronics of Seville, Spain |
|
| 11:45 - 12:15 |
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CD11
Automated flow used to fill white space with very high density 3D capacitors for efficient decoupling capability in the RF domain
NXP
|
Continue
Digital Implementation Roadmap
|
FV11
Advanced Stimuli Modeling Using e Sequences
Cadence Design Systems
|
SD&V05
Usage of Palladium -III for DDR/DDR2 verification in complex SoCs
STMicroelectronics
|
SPB11
Link between SiP and Microwave Studio
CST/Cadence Design Systems
|
AC12
Implementation of widespread IC design skills in advanced deep submicron technologies at European Academia
IMEC, Belgium |
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| 12:15 - 12:45 |
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CD12
Integrated DC/DC converter stability analysis using PSTB
Lehrstuhl für Integrierte Analogschaltungen
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DI12
Improving advanced node DFM/DFY design flows through analysis engine integration.
Cadence Design Systems
|
FV12
Mixed Signal Verification - are SystemVerilog-AMS Assertions the future ?
Texas Instruments
|
SD&V06
Coverage Driven Verification applied to Embedded Software
University of Tuebingen
|
SPB12
Rhapsody and PCells for RF SiP
Cadence Design Systems
|
AC13
Functional Performance Modeling for wireless LAN SoCs
Univ of Paderborn, Germany |
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| 12:45 - 13:15 |
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CD13
Verification Methodology of Analog and Mixed Signal Circuits Considering Operating Areas (SOA) Constraint concepts
ZMD
|
DI13
DUTY: A new approach of DFM/DFY methodology
Atmel
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FV13
It's a Mixed Signal World: Mixed Signal Simulation and Verification Methodology Today
Cadence Design Systems
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SD&V07
Implementing a Complete Low Power Flow from Architecture to GDSII
Cadence Design Systems
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AC14
ARM University Program
ARM
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| 13:15 - 14:30 |
Lunch and Best Paper Presentations |
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NOTE: Agenda is subject to change.