Home > CDNLive! > EMEA > 2009 > Agenda - Tuesday

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Conference Agenda : Tuesday, May 19
07:30 - 08:30 Breakfast & Registration  
     
8:30 - 9:15 Keynote: Succeeding in Today's Dynamic Electronics Industry
Lip-Bu Tan, President and Chief Executive Officer, Cadence Design Systems, Inc.
     
9:15 - 10:00 Industry Keynote: ARM Business Environment and Strategy
Ian Drew, EVP Marketing, ARM 		 
     
10:00 - 10:30 Coffee Break  


10:30 - 11:00  
Custom Design
Track		 Digital Implementation
Track		 Functional Verification
Track		 Logic Design
Track		 Silicon-Package Board
Track		 Academic
Track
CD01
Process Design Kit for a modular technology platform exploiting new ITDB infrastructure.
STMicroelectronics		 DI01
The ART of IC Design - Pushing the limits
NEC 		FV01
Re-using OVM test benches for verifying the integration of modules into a system
NEC 		LD01
Formally Verifying Clock Domain Crossings in Lock-Step Safety Devices Using LEC CDC and IFV
Freescale Semiconductor 		SPB01
PCB/SPB Roadmap		 AC01
An open platform for Low Power VLSI design research and teaching
Technical University of Braunschweig, Germany


11:00 - 11:30    
CD02
First project experience with the IC6.1.3 environment
Austria Micro Systems		 DI02
Using CCD to filter critical paths for @speed pattern generation
Freescale Semiconductor 		FV02
IP Integration Verification using the OVM and Cadence AHB/AXI UVCs
NEC 		LD02
Verifying Your SDCs from RTL to P&R – Two Customer Examples
Cadence Design Systems 		Continue
PCB/SPB Roadmap		 AC02
Advanced Verification in the Implementation of Large Research Projects
University of Heidelberg, Germany
University of Bristol, UK


11:30 - 12:00    
CD03
X-FAB's methodology for design kit- and project- migration to IC6.1
X FAB		 DI03
Tape-out while you sleep: towards an automated ECO generation flow for faster design closure
Silicon & Software Systems 		FV03
Functional Verification Roadmap 		LD03
Early Exploration of Network Processor Architectures Using Cadence InCyte Chip Estimator
Heinz Nixdorf Inst 		SPB02
Creepage Distance Analysis on PCBs with NEXTRA
Mecadtron GmbH 		AC03
Frequency Compensation by Automated Topology Modification Using Mixed Analytical and Numerical Methods for Design of Fast Optoelectronic Applications
Ilmenau University of Technology
Institute for Microelectronic and Mechatronic Systems (IMMS) gGmbH, Germany


12:00 - 12:30    
CD04
A Novel EDA-Compatible Methodology for Design and Simulation of MEMS with IC
Coventor 		DI04
Device Configuration and Memory Repair Architecture for Embedded Micro Controllers
Freescale Semiconductor 		Continue
Functional Verification Roadmap 		LD04
CoReUse and Qcore: Reuse and safeguard IP
NXP 		SPB03
New Technologies for 6 Gbps Serial Link Design & Simulation, a Case Study
Siguys.com 		AC04
Toward 4G Nanometer Radio Receivers: Design Methodology and a Case Study
KTH Stockholm, Sweden


12:30 - 13:45 Lunch  


13:45 - 14:15    
CD05
Verification of High Performance ADC in IC61
Arctic Silicon Devices 		DI05
Improving Clock Distribution Quality Through Early Visualization
Freescale Semiconductor 		FV04
Efficient and Exhaustive Verification: possible or dream?
FBE Asic 		LD05
Logic Design Roadmap 		SPB04
Post Layout EMC Analyses for PCBs
SimLab Software GmbH 		AC05
Methodology Comparison for Designing MEMS Sensor Read-Out Circuits
University of Freiburg, Germany


14:15 - 14:45    
CD06
Open Command Environment for running Advanced Analysis of Mixed Signal circuits (OCEAN-XL)
Cadence Design Systems 		DI06
Enabling low perturbation ECOs in Post DFM advanced node designs
Cadence Design Systems 		FV05
Managing a complex SoC verification project with eManager!
Freescale Semiconductor 		Continue
Logic Design Roadmap 		SPB05
High Density Interconnect (HDI)
FlowCAD 		AC06
RAL Microelectronics Design and Support Centre
STFC Rutherford Appleton Laboratory, UK


14:45 - 15:15 Coffee Break  


15:15 - 16:15    
Custom Design
demo
Speed up your Spectre/MultiMode Simulation without sacrificing accuracy and no change in the use model 		Digital Implementation
demo
Increasing Mixed-Signal Designer Productivity using Virtuoso and Encounter Technology		 Functional Verification
demo
New Debug Features in Specman/Incisive Enterprise Simulator XL		 System Design & Verification demo
Next-Generation High-Level Synthesis (HLS) to Enable TLM-Driven Design and Verification 		Silicon-Package Board
demo
A Unique FPGA-PCB Co-Design Solution 		Language & Methodology / Hands-On (run by Education Services)
TLM - Head Start


16:15 - 17:15    
Custom Design
demo
Next-generation Mixed-Signal Simulation 		Digital Implementation
demo
CPF-Enabled Cadence Low-Power Solution		 Functional Verification
demo
Metric-Driven Verification with Assertion-Based Verification 		System Design & Verification demo
Using Fast Models from ARM with Incisive Technology for Verification and Analysis 		Silicon-Package Board
demo
High-Density Interconnect (HDI) Design		 Language & Methodology / Hands-On (run by Education Services)
Advanced Specman - Integrating UVC\'s into larger environments and how Aspect Orientation helps productivity


17:15 - 18:15    
Custom Design
demo
Virtuoso Custom Design Platform 6.1.3 – the Art of Engineering, Amplified		 Digital Implementation
demo
Design at Advanced Nodes with the New Encounter Digital Implementation System		 Functional Verification
demo
Next-Generation Coverage Contribution using Formal Analysis		 System Design & Verification demo
Third-Party Virtual Platform Integration with Incisive Technology		 Silicon-Package Board
demo
Achieve Shorter, More Predictable Design Cycles with an RF-Aware PCB Design Environment 		Language & Methodology / Hands-On (run by Education Services)
SystemVerilog OVM (Open Verification Methodology)- Head Start


18:15 - 23:00 Evening event at Hilton  


Hardware Demos at Cadence Booth in Expo area
- Complete ARM-Based HW/SW Co-Verification Environment using Palladium III
- Transaction-Based Acceleration for an Ethernet-Based Design using Xtreme III
- System-Level Power Analysis with Palladium III / Dynamic Power Analysis
- Emulation of Wireless SoCs with Palladium III and a Protocol Tester
- Compliance Management System demo using Cadence Incisive Verification IP

NOTE: Agenda is subject to change.