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Conference Highlights
CDNLive! EMEA 2009 — Conference Highlights

CDNLive! EMEA, May 18-20 in Munich, brought together over 480 Cadence® technology users, developers, and industry experts to educate and energize at the premier technology conference in the EMEA region. Customers from over 200 European and international companies spent two and a half days participating in user presentations, Cadence demos and techtorials and visiting partners in the EDA ecosystem at the Designer Expo.

Monday 18th May

The conference opened its doors on Monday 18th May with five techtorials taking place in the afternoon covering topics on:

Custom Design
Part 1: Constraint-Driven Design Using Virtuoso IC 6.1
Part 2: Using Virtuoso Multi-Mode Simulation 7.1 – Spectre RF to Dramatically Enhance Productivity
Part 3: Analyzing, Preventing, and Correcting the Impact of Manufacturing Variation in Advanced-Node IC Design, Including Physical and Electrical Effects Induced by Litho, CMP, and Stress

Digital Implementation
Design Closure for Large-Scale, High-Performance Designs

Functional Verification
OVM in a Multi-Language World

System Design and Verification
System-Level Design and Chip Architecture for Low-Power ICs

Silicon-Package Board Co-Design
Low-Power Strategy for SiPs - A Co-Design Solution for Power Delivery on Package followed by A Unique FPGA-PCB Co-Design Solution.

During the breaks and evening networking event, attendees had the opportunity to visit the Designer Expo and meet with Cadence partners across the electronics industry.

Tuesday 19th May

Cadence President and CEO, Lip Bu Tan, commenced the second day with a keynote discussing how to “Succeed in Today's Dynamic Electronics Industry”. He discussed the issues of adapting to new trends, as well as the role that Cadence plays in delivering predictability, productivity, and reliability in product design. The guest keynote was Executive Vice President of ARM Marketing, Ian Drew, who discussed ARM’s Business Environment and Strategy.

During the keynote session, Lip-Bu also took the opportunity to congratulate the winners of the EMEA Universities contest for the “Fastest Custom Layout Designer of the Year”. Co-winners Américo Dias and Daniel Oliveira of the Microelectronics Students' Group of the University of Porto, Portugal, were presented a prize by Lip-Bu Tan which included free training sponsored by Cadence Education Services.

The rest of the morning and early afternoon consisted of a multitude of customer and Cadence presentations in six Technical Tracks on Custom Design, Digital Implementation, Functional Verification, Logic Design, Silicon-Package-Board and an Academic Track was also running. Executive and press attendees attended the Executive Track and the Press Track respectively.

During the afternoon, demonstrations of the latest Cadence products, flows, and methodologies were shown in each of the tracks. The Logic Design Track ended and the System Design & Verification track began with demos and continued with user papers on Wednesday.

Tuesday concluded with an energetic evening event. A surprise "high-energy show" lifted spirits and, in addition, two pedal bikes generated a huge amount of interest for a competition in which attendees rode the bikes to create electricity. The person who generated the most “energy” in 20 seconds won the grand prize.

Wednesday 30th April

On the last day of the conference more customer presentations were held in the six technical tracks and the academic track, and the best paper for each track, as voted by the conference attendees, was awarded a prize by Wolfgang Stronski, Field Marketing Director EMEA.


 
CDNLIVE! EMEA 2009 — BEST PAPER AWARDS

Attendees at the CDNLive! EMEA 2009 event took part in voting for the best papers in each major category. We are pleased to announce the winners for each of the following tracks:

Custom Design Track

A Novel EDA-Compatible Methodology for Design & Simulation of MEMSwith IC
Gunar Lorenz, Coventor

Digital Implementation Track

Implementing Cortex-A9 Multicore Processors for High-Performance and Low-Power Requirements at 65nm and below using ARM-Cadence IRM
Kinjal Dave, ARM

Logic Design Track

Early Exploration of Network Processor Architectures using Cadence Incyte Chip Estimator
Christian Liss, University of Paderborn

Functional Verification – joint winners

Moving from Direct Testing to metric-driven Verification by Utilizing Verification IP: A Case Study
Sarmad Dahir and Michael Carlberg, Ericsson
Managing a Complex SoC Verification project with eManager
Jochen Fader, Freescale Semiconductor

System Design & Verification

System Validation of the Cortex-A9 Processor
Bryan Dickman, ARM

PCB & IC Packaging

Design Constraints for PCB with Gbit Serial Links
Rolf Nick, FlowCAD

Academic Track

Frequency compensation by Automated Topology Modification Using Mixed Analytical and Numerical Methods for design of fast optoelectronic applications
Professor Doctor Ralf Sommer, IMMS/Technical University of Ilmenau

 
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CDNLive! EMEA
May 18-20
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