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Conference Agenda : Monday, May 18
12:00 Registration opens  
     
12:00 - 13:30 Designer Expo / Light Lunch Buffet  


13:30 - 15:30    
Custom Design
Techtorial
Part 1: Constraint-Driven Design Using Virtuoso IC 6.1

Part 2: Using Virtuoso Multi-Mode Simulation 7.1 – Spectre RF to Dramatically Enhance Productivity

Part 3: Analyzing, Preventing, and Correcting the Impact of Manufacturing Variation in Advanced-Node IC Design, Including Physical and Electrical Effects Induced by Litho, CMP, and Stress 		Digital Implementation
Techtorial
Design Closure for Large-Scale, High-Performance Designs 		Functional Verification
Techtorial
OVM in a Multi-Language World		 System Design and Verification Techtorial
System-Level Design and Chip Architecture for Low-Power ICs
- Chip planning, estimation, analysis; including pre-RTL power tradeoffs
- HLS of C/C++/SystemC models for Low Power
- RTL-Based Design Exploration of Timing, Power, Area
- SoC Dynamic power analysis with real-world stimulus 		Silicon-Package Board
Co-Design Techtorial
Part 1: Low-Power Strategy for SiPs - A Co-Design Solution for Power Delivery on Package

Part 2: A Unique FPGA-PCB Co-Design Solution


15:30 - 16:00 Coffee Break  


16:00 - 17:30    
Custom Design
Techtorial (continued)		 Digital Implementation
Techtorial (continued)		 Functional Verification
Techtorial (continued)		 System Design and Verification Techtorial (continued) Silicon-Package Board
Co-Design Techtorial (continued)


17:30 - 20:30 Networking Evening  


Hardware Demos at Cadence Booth in Expo area
- Complete ARM-Based HW/SW Co-Verification Environment using Palladium III
- Transaction-Based Acceleration for an Ethernet-Based Design using Xtreme III
- System-Level Power Analysis with Palladium III / Dynamic Power Analysis
- Emulation of Wireless SoCs with Palladium III and a Protocol Tester
- Compliance Management System demo using Cadence Incisive Verification IP

NOTE: Agenda is subject to change.