Home > About Cadence > Customer Success > Customer Success

Share
  • Email
  • Social Web
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Customer Success 
Latest Success Stories
By Category  
Fuji Electric
Business Challenges
Aggressive time-to-market requirements for a new low-power, low-noise, low-cost power-supply IC
Design Challenges
Required complex verification items
Needed to increase efficiency of concept design
Cadence Solutions
Virtuoso Multi-Mode Simulation with the Accelerated Parallel Simulator
Virtuoso Analog Design Environment
Results
Reduced design lead time by approximately 25% with SPICE-accurate simulation
Met time-to-market goals with a highquality product
Achieved scalable performance and capacity
Improved verification performance by 26x
Improved simulation performance by 2x
 Read Full story»
Texas Instruments
Business Challenge
Short time-to-market window for complex mixed-signal design verification
Design Challenges
High-performance, ultra low-power features in close interaction with core analog functional blocks at the SoC level
High-volume product
Functional failures would lead to costly design iterations
Cadence Solutions
Digital-centric mixed-signal verification flow
Incisive Enterprise Simulator Digital/Mixed-Signal (DMS) Option
Incisive Enterprise Specman Elite Testbench
Incisive Enterprise Manager
Virtuoso AMS Designer with flexible analog simulation
Virtuoso Accelerated Parallel Simulator – XL
Customer Support
Results
300x faster verification vs. mixed-signal simulation at the transistor level
Improved time to market and product quality with mixed-signal regression runs
Fewer re-spins with high-performance, real-number modeling and top-level, metric-driven mixed-signal SoC verification
Earlier detection and correction of errors
10x cycle-time improvement in mixed-signal verification
 Read Full story»
QLogic
Business Challenges
Quickly produce a sophisticated new network switch to capture market share
Design Challenges
Ensure success of complex ASIC design with system-level verification
Cadence Solutions
Palladium XP Verification Computing Platform
Customer Support
Results
Achieved verification of an ASIC design at the system level, earlier in the design cycle and faster than in previous ASIC verification projects
Reduced verification time by 50% compared to previous, less-complex switches
 Read Full story»
Freescale Semiconductor
Design Challenges
Mixed-signal design with new flash technology and new ARM Cortex-M4 core
10 different power modes ranging from high-performance through very low leakage standby mode
Advanced techniques like innovative back-biasing scheme and multi-length gate libraries
Cadence Solution
Full low-power flow including power-aware simulation, synthesis and scan insertion, physical design and formal verification
 Read Full story»
LSI Corporation
Business Challenges
Establish a proven mixed-signal methodology to verify analog IP for a mixed-signal chip
Produce a high-quality product in a short time-to-market window
Design Challenges
Upgrade ad-hoc, manual verification methodology for analog IP
Leverage current, optimal verification flow for digital IP
Cadence Solutions
Incisive Enterprise Simulator
Incisive Enterprise Manager
Incisive Enterprise Specman Elite Testbench
Virtuoso AMS Designer
Virtuoso Schematic Editor
Virtuoso Analog Design Environment
Customer Support
Results
Established a methodology that can be extended to analog verification
Expanded analog design verification coverage and improved product quality
Met design and performance specifications
 Read Full story»
TowerJazz
Business Challenges
Time-to-market pressures
Rising development costs
Design Challenge
Product differentiation and customization for analog and mixed-signal specialty products
Cadence Solutions
Virtuoso unified custom/analog flow
Virtuoso Layout Suite
Virtuoso Analog Design Environment
Virtuoso AMS Designer
Virtuoso Spectre Circuit Simulator
Virtuoso Space-Based Router
Cadence QRC Extraction
Cadence Services
Results
Complete, customized offerings with a wide array of tools and functions
Lower development costs
Faster time to market
 Read Full story»
Technical University of Braunschweig
Challenges
Prepare students for workforce by teaching with powerful electronic design automation (EDA) technologies
Cultivate relationships with educators and corporations to further academic research in low-power digital design
Cadence Solutions
Cadence Academic Network
Incisive Unified Simulator
Encounter RTL Compiler
Encounter Digital Implementation System
3D Design Viewer
C-to-Silicon Compiler
Results
Students earn internships and jobs at leading technology companies with a strong presence in Europe
TUBS participates in publicly funded research projects involving low-power digital design
 Read Full story»
IBM
Business Challenges
Increasingly stringent specifications
Increasing complexity of sub-micron technologys
Design Challenges
Generate a robust model qualification flow for IBM SOI process nodes
Achieve first-pass design success with high correlations between silicon and circuit verification using advanced SPICE models
Cadence Solutions
Cadence Virtuoso Spectre Circuit Simulator
Cadence Virtuoso Multi-Mode Simulation
Results
Reduced overall SOI model validation cycle time for new compact model code by up to 30 percent
Improved productivity and SOI process node accuracy
 Read Full story»
Kilopass Technology
Design Challenge
Boost layout productivity
Improve communication between designers and implementation engineers
Quickly migrate from one process node for a given foundry to the next generation using a standard CMOS process

Cadence Solution
Virtuoso unified custom/analog flow (6.1)
OpenAccess database
 Read Full story»
VeriSilicon
Design Challenges
Accelerate the design process with automated, placement-aware pin assignment
Optimize the physical connectivity, even as it changes
Ensure quality and reduce complexity with reuse of interface rules and protocols

Cadence Solution
Allegro FPGA System Planner XL
 Read Full story»
 
Next »