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Hitachi
Toru Hiyama
Hitachi

In this 2-minute video, Hitachi's Toru Hiyama, general manager, Global MONOZUKURI Division, explains how using Cadence® high-speed verification tools, including the Protium™ and Palladium® XP platforms, helps the company achieve faster bring up and overall shorter time to market of its embedded software systems.
SiriusXM
Daniel Morera
SiriusXM

At SiriusXM, engineers develop satellite radio baseband devices that use higher density and higher frequency DDR3 memory. The company's latest design more than doubled the density and clock rate of previous designs. In this 3-minute video, hear Daniel Morera, a hardware engineer at SiriusXM, highlight the benefits the company gained by using Cadence® Sigrity™ tools to simulate and optimize the DDR3 interface before releasing their boards.
ams
Bertram Winter
ams

At ams AG, the engineering team had been performing electromigration checks at signoff. As a result, problems were detected late in the cycle, so the team had to make additional efforts to fix these problems. This was a costly approach that could potentially delay the project. Watch this short Expert Insights video to hear Bertram Winter, a design support engineer at ams, explain how Cadence's electrically aware design flow helped the team revamp its process to avoid additional design iterations.
Freescale
Julia Perez
Freescale

Freescale introduced constraint-driven design into its environment in 2014 and in that year, completed more than 700 runs using customized constraint bundles developed with SKILL API. Julia Perez, a PDK/CAD developer at the company, is responsible for automation and adoption of constraint-driven design for analog technologies. Watch this video to hear Perez talk about lessons learned and successes achieved with constraint-driven design using Cadence® Virtuoso® Schematic Editor XL and Cadence Virtuoso Layout Suite XL.
RushC
Andy Fox
RushC

Andy Fox is CEO of RushC, a hardware and software consulting company. Needing to evaluate co-processor architectures for DSP applications, RushC turned to SystemC and high-level synthesis. Using Cadence's Stratus High-Level Synthesis platform, the company generated RTL from C/C++/SystemC source code and using Cadence's Encounter® tools, the company was able to evaluate the PPA using the RTL. Watch the video to learn why the company found it easier to design with SystemC than with Verilog.
Freescale Semiconductor
Abhinav Nawal
Freescale Semiconductor

Watch this 3-minute video to learn how Freescale verifies its next-gen low-power SoC with Cadence® power-aware x-optimism simulation. Abhinav Nawal, a member of the company's SoC verification team, walks you through the process.
Cavium
Bill Munroe
Cavium

Routing boards with high-speed interfaces had been a time-consuming, manual process at Cavium. To alleviate scheduling pressures without sacrificing quality of their multi-layer boards, the San Jose, CA, semiconductor company automated the process with the Cadence® Allegro® TimingVision environment. In this 3-minute video, Bill Munroe, principal PCB designer in the company's Post-Silicon Group, talks about how the technology helped his team achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems.
Freescale Semiconductor
Sorabh Sachdeva
Freescale Semiconductor

Watch this 2-minute video to hear Sorabh Sachdeva, a design engineer at Freescale Semiconductor, explain how he and his team used Cadence® Virtuoso® Schematic Editor to solve their verification challenges on their mixed-signal, low-power, multi-voltage SoCs.
Tejas Networks
Amba Prasad
Tejas Networks

In this short video, Amba Prasad, product architect, R&D, at Tejas Networks, explains how the IPC-2581 design data format and Cadence® Allegro® tools eliminate surprises at the final stages of PCB design. These technologies are helping Tejas Networks deliver high-quality products faster than their competitors.
Freescale Semiconductor
Nikhil Murgai
Freescale Semiconductor

Routing and timing closure were big challenges on the high-performance cores developed by Freescale Semiconductor. How did the engineers improve these processes? Watch this video to hear Nikhil Murgai, lead design engineer at Freescale Semiconductor, talk about how the team used Cadence® Encounter® digital implementation tools to save routing resources and speed up the timing closure process.
 
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