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Freescale Semiconductor
Nikhil Murgai
Freescale Semiconductor

Routing and timing closure were big challenges on the high-performance cores developed by Freescale Semiconductor. How did the engineers improve these processes? Watch this video to hear Nikhil Murgai, lead design engineer at Freescale Semiconductor, talk about how the team used Cadence® Encounter® digital implementation tools to save routing resources and speed up the timing closure process.
ARM
Robert Kaye
ARM

Creating a virtual prototype becomes more challenging when graphics cores are involved because they have different instruction sets than CPUs. Watch this video to hear Robert Kaye, technical specialist with the Development Solutions Group at ARM, share tips and techniques for creating hybrid virtual platforms with the Cadence® Palladium® XP platform and accelerated verification IP.
National Instruments
George Zafiropoulos
National Instruments

From algorithms to pre- and post-silicon validation and test, the chip design process is supported by a variety of tools and methodologies. But, as you may well know, the process isn't always very efficient. In this 4-minute video, George Zafiropoulos, vice president of Solutions Marketing at National Instruments, talks about working with Cadence to develop a more efficient chip design flow. Hear what George has to say about what happens when a prototyping platform like Cadence's Palladium® environment is connected with National's test environment for full-chip validation.
Nexus Technology
Joe Socha
Nexus Technology

At Nexus Technology, Joe Socha, signal integrity engineer, is responsible for analyzing tiny PCBs that are used as interposers between memory devices and their target systems. Probing memory devices can be difficult, but an interposer allows the engineer to gain signal access. In devices such as DDR4 and LPDDR4, there are electrical and mechanical challenges that Nexus manages by using Cadence® Allegro® and Sigrity™ tools. In this video, Socha talks about how the Cadence Sigrity PowerSI® tool enables the team to run what-if cases to gain insights that lead to useful changes in trace widths, impedance, and more.
Allegro Microsystems
Khalid Chishti
Allegro Microsystems
 
In this Expert Insights video from CDNLive Boston 2014, Khalid Chishti, verification manager at Allegro Microsystems discusses how his automotive speed sensor mixed-signal IC project had many verification challenges causing inefficiencies and slowing time to market. They were able to get back on track with Cadence's Incisive® vManager™ solution, which provided a more powerful approach for combined digital and mixed signal verification, improving verification efficiency and productivity.
Ericsson
Sheetal Jain
Ericsson

In this video from CDNLive India 2014, Sheetal Jain, a member of the modem organization at Ericsson Design, discusses how his team verified their design to meet DDR and PCIe specs while avoiding crosstalk. They were able to simulate and verify using Cadence's Sigrity™ solution with the IBIS/AMI virtual reference design for interface compliance signoff, which they found to be easy to set up and easy to test, while saving them time and money.
MegaChips
Suryansh Sahota
MegaChips

MegaChips found that its traditional ECO methodology was not producing the results needed. In this video, Suryansh Sahota, a design engineer at the company, talks about how a physically aware ECO methodology based on Cadence's Tempus™ Timing Signoff Solution and Encounter® Digital Implementation System yielded far better TAT, power consumption, and elimination of DRV, setup, and hold violations.
Open-Silicon
Tilak Miryala
Open-Silicon

Open-Silicon develops complex chips with millions of gates, thousands of clocks, as well as repeatable blocks. Timing signoff and constraints validation can be quite challenging. Tilak Miryala, a design engineer at the company, talks about the limitations of a traditional ECO flow, the advantages of a traditional physically aware ECO flow, and, finally, the benefits of an MC-ECO flow available in the Cadence® Encounter® Digital Implementation System and Tempus™ Timing Signoff Solution.
MegaChips
Designing a networking chip with a hierarchical design can be very challenging in terms of timing correlation between synthesis and implementation and congestion after scan insert. Raghavendra Prasad, a senior design engineer at MegaChips, talks about how much measurable improvement the company gained by applying physically aware synthesis with Cadence® Encounter® RTL Compiler with Physical. Watch the video to learn how to avoid surprises in layout.
PMC
Using a traditional FPGA-based prototyping solution, PMC experienced system bring-up times that lasted from a week to two months. To speed up the process, while also using their existing Cadence® Palladium® XP environment, PMC migrated to the Cadence Rapid Prototyping Platform. Now, they can bring up a system in as little as a week and a half. Yogendra Pal, technical manager for product verification, and Ramchandra Vibhute, a staff engineer, tell you how in this 3-minute video.
 
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