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Fairchild Semiconductor
Watch this 1 1/2-minute video to hear how Chris Bennett, ASIC layout engineer at Fairchild Semiconductor, solved a floorplanning challenge in a mixed-signal design using Cadence® Virtuoso® custom design and Cadence® Digital Implementation platforms. Routing power to hard macros inside the digital portion of the design was difficult, until the team began using the combined Cadence mixed-signal implementation solution, which also helped assure them that they would meet their EMIR requirements.
NXP
Santhosh Kumar
NXP

NXP's ultra-low power designs have multiple power and voltage domains, making signoff exceptionally challenging. Watch this 2.5-minute video to hear Santhosh Kumar, a senior design engineer at NXP, explain how Cadence's concurrent and distributed MMMC flows help the team overcome their challenges by consolidating all of their timing inputs into one group. ​.​
eInfochips
Nilesh Ranpura & Dhaval Parikh
eInfochips

Designing a large-scale SoC? Watch this 3-minute video to hear how Nilesh Ranpura, a project manager at eInfochips, and Dhaval Parikh, sr. tech lead, physical design, for the company, shortened runtime and improved productivity on a three SoC platform with 300M gate counts. Their main worry was meeting the 12-month delivery schedule, but they alleviated their concerns using the Cadence® Innovus™ Implementation System. Learn from the best practices they share in this video​.​
PMC-Sierra
Hanumantharaya H
PMC-Sierra

While designing a large SoC with hierarchical blocks, PMC-Sierra uncovered a need for a user interface language that could access design and DFT objects from an ATPG database. Watch this 3-minute video to hear why Hanumantharaya H, a DFT technical leader at the company, believes that an extension language-based utility is the answer to providing testability status for each interconnect in a DFT block. The company used the extension language capabilities in Cadence® Encounter® Test​.​
PMC-Sierra
Vinayak Bhat
PMC-Sierra

Watch this 2-minute video to hear Vinayak Bhat, a staff mixed-signal verification engineer at PMC-Sierra, explain how he and his team improved timing characterization of analog macros using Cadence® Virtuoso® Liberate™ AMS Mixed-Signal Characterization Solution. With a timing path buried deep in the hierarchy and too many manual interventions, the team revamped its processes using the Virtuoso tool.
Seagate
Subramian Ramanathan
Seagate

The ECAD team at Seagate Technology was building a 5U chassis, but due to its multiple interconnected boards and cables, it was a challenge to understand the IR drop and system challenges. Subramian Ramanathan, Sr. Engineering Manager, and Shashi Singh, Hardware Engineer, describe how they used the Cadence® Allegro® schematic and layout technology with the Cadence Sigrity™ PowerDC™ tool for simulation. These tools gave results immediately, allowing modifications to the layout to lower IR drop before sending to review, ultimately accelerating review cycles and lowering overall cost.
Open-Silicon
Pradeep Sukumaran
Open-Silicon

Pradeep Sukumaran, a sr. solutions architect at Open-Silicon, is responsible for driving the company's IoT backbone strategy. In this 4-minute video, Sukumaran talks about building an end-to-end system with IoT edge device ASICs, and explains how using the Cadence® Tensilica® Fusion DSP helped Open-Silicon address power consumption and security concerns.
Nvidia
Melanie Bianchi
Nvidia

At Nvidia, Melanie Bianchi, NVLink emulation lead at the company, is responsible for IP acceleration efforts. In this 2-minute Expert Insights video, Bianchi explains how using the Cadence® Palladium® XP verification computing platform enabled the company to achieve higher level testing and enhance debug of its custom ARM® core environment. Bianchi and her team were also able to boot the OS and run live applications on the Palladium XP platform, which helped boost their confidence in their design.
MCCI Corporation
Terry Moore
MCCI Corporation

Terry Moore, CEO and founder of MCCI Corporation, explains USB Type-C and how it will provide flexibility, convenience, and power to future products and their development. This one easy-to-use and technology-flexible USB Type-C connector will replace the various types of connectors that devices currently use to interact. Developing with this new connector will allow product designers to focus on their unique creations, while using partner IP and off-the-shelf components for things like power supplies, thereby improving time to market and return on investment.
PMC
Riad Ben Mouhoub
PMC

Riad Ben Mouhoub, a staff engineer at PMC Sierra, works on a team that develops chips for the enterprise storage market. In his role, he's well acquainted with system-level verification challenges : increasing design size and complexity, time-to-market pressures, and the fact that verification cycles can outweigh design times, to name a few. In this short video, Mouhoub explains how implementing the Cadence® Palladium® XP verification computing platform along with Cadence SpeedBridge® Adapters enabled PMC Sierra to test their DUT with real-world data that can't be modeled on a testbench, achieve bring-up in less than a week with a runtime more than 10,000X faster than a simulation-based approach, and find critical bugs that a pure simulation approach would have missed.
 
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