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Customer Success Videos 

Latest Success Videos
By Category  
MediaTek
Andrew Chang
MediaTek

In this video, Andrew Chang, MediaTek corporate vice president, talks about the challenges in creating today's smart devices—complexity, the push for higher performance, and the need for lower power. Chang discusses how the Cadence® Palladium platform has helped MediaTek achieve faster simulation and debug; the company has achieved a 300X speed-up in simulation time, with 6X faster turnaround time. As a result, MediaTek is succeeding in meeting its time-to-market and design quality goals.
PMC
Vivekanand Malkane
PMC

Engineers at PMC were frustrated with their slow, manual process for verifying analog IP and developing functional models. To automate its processes, the company implemented Cadence® Virtuoso® Schematic Editor and a SystemVerilog testbench. In this video, Vivekanand Malkane, technical manager of the mixed-signal verification team at PMC, talks about how much more efficient the team's verification process is.
STMicroelectronics
Livio Frantantonio
STMicroelectronics

STMicroelectronics relies on mixed-signal solutions for its Smart Power Technologies. As Livio Frantantonio explains in this video, STMicro needed to increase productivity and quality of results while shortening its turnaround times. The company found its answer in Cadence's mixed-signal solutions, including Virtuoso® Mixed-Signal Flow. Watch this video to learn how STMicro benefited from using the Cadence Unified Mixed-Signal Methodology.
Altair Semiconductor
Noam Meser
Altair Semiconductor

For Altair Semiconductor, which develops SoCs for smartphones and tablets, fast time to market is critical. Verifying its SoC architecture can be challenging, but the company addressed this with a verification flow based on Cadence® Incisive® Enterprise Simulator, the IEEE 1647, e language, and vManager for regression runs. Noam Meser, system level verification lead at the company, tells why he is "addicted" to Cadence.
NXP
Rajesh Chitturi
NXP

NXP strives to deliver bug-free products such as RFID, NFC and smart card SoCs. Watch this video to learn how design engineer Rajesh Chitturi worked with his team to save 1.5 weeks from their verification cycle while increasing code coverage to 95% using a flow based on Cadence® Incisive® Enterprise Manager, Incisive Enterprise Verifier, and Incisive Metric Center.
Freescale
Paresh Joshi
Freescale

Freescale wanted to augment its simulation process for longer running test cases, enable its software teams, and have performance validation (for latency, bandwidth, and throughput) in place. Watch this video to hear Paresh Joshi, a principal staff design engineer at the company, explain how the Cadence® Palladium® XP platform met all of these requirements while helping Freescale speed its simulation process and achieve faster builds.
Analog Devices
Eduard Raines
Analog Devices

Watch this video to learn how Analog Devices ramped up engineering productivity using ModGen tools in Cadence's Virtuoso® Layout Suite solution. CAD engineer Eduard Raines explains how his team replaced time-consuming manual processes with an automated solution to create custom programs for high performance, highly matched design structures.
Freescale
Abhinav Nawal
Freescale

Abhinav Nawal from Freescale stepped above the traditional directed test approach for (Common Power Format) CPF low-power verification. He used Cadence® Incisive® Enterprise Manager, Incisive Enterprise Simulator, SimVision debug, and the Incisive Metric Center to find many critical system-level corner case issues, which, left undetected, would have been catastrophic for his SoC.
Analog Devices
Sri Ranganayakulu
Analog Devices

Sri Ranganayakulu from Analog Devices applied the Cadence® Incisive® X-propagation simulation and SimVision debug capabilities to speed up reset verification. In this video, he talks about how he caught eight bugs in two designs in less time than it took with the traditional gate-level approach.
STMicroelectronics
Mohit Jain
STMicroelectronics

Mohit Jain from STMicroelectronics applied Cadence® Incisive® Enterprise Simulator and SimVision debug capabilities for IEEE 1801 / UPF low-power verification to a low-power demonstrator in preparation for use with a production set-top box chip. Watch this video to learn how he reused his existing code successfully, including the power format files and the macro models coded in his Liberty files.
 
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