Home > About Cadence > Customer Success > Customer Success Videos

Customer Success Videos 

Latest Success Videos
By Category  
Nvidia
Melanie Bianchi
Nvidia

At Nvidia, Melanie Bianchi, NVLink emulation lead at the company, is responsible for IP acceleration efforts. In this 2-minute Expert Insights video, Bianchi explains how using the Cadence® Palladium® XP verification computing platform enabled the company to achieve higher level testing and enhance debug of its custom ARM® core environment. Bianchi and her team were also able to boot the OS and run live applications on the Palladium XP platform, which helped boost their confidence in their design.
MCCI Corporation
Terry Moore
MCCI Corporation

Terry Moore, CEO and founder of MCCI Corporation, explains USB Type-C and how it will provide flexibility, convenience, and power to future products and their development. This one easy-to-use and technology-flexible USB Type-C connector will replace the various types of connectors that devices currently use to interact. Developing with this new connector will allow product designers to focus on their unique creations, while using partner IP and off-the-shelf components for things like power supplies, thereby improving time to market and return on investment.
PMC
Riad Ben Mouhoub
PMC

Riad Ben Mouhoub, a staff engineer at PMC Sierra, works on a team that develops chips for the enterprise storage market. In his role, he's well acquainted with system-level verification challenges : increasing design size and complexity, time-to-market pressures, and the fact that verification cycles can outweigh design times, to name a few. In this short video, Mouhoub explains how implementing the Cadence® Palladium® XP verification computing platform along with Cadence SpeedBridge® Adapters enabled PMC Sierra to test their DUT with real-world data that can't be modeled on a testbench, achieve bring-up in less than a week with a runtime more than 10,000X faster than a simulation-based approach, and find critical bugs that a pure simulation approach would have missed.
ARM
Brent McKanna
ARM

ARM's Brent McKanna, a senior principal design engineer, leads the company's CPU implementation video. In this 2-minute video, McKanna talks about how ARM and Cadence worked together to address the challenges of developing the ARM Cortex-A72 processor at 16nm. From changing process rules and IP to tool readiness and routability concerns, the teams overcame the challenges, using Cadence® Encounter® and Innovus™ technologies to develop a higher performing, lower power processor. Now, the companies are ready to tackle the challenges of 10nm.
Freescale Semiconductor
Regis Santonja
Freescale Semiconductor

Regis Santonja, Senior Mixed-Signal Verification Engineer, Freescale Semiconductor discusses the challenge of drastically reducing the size of an accelerometer without compromising performance in terms of current consumption and noise, as well as transitioning to a UVM mixed-signal environment to introduce randomization to system-level simulations. By using Cadence® Incisive® vManager™ Solution to run and analyze thousands of simulations before tapeout, his team discovered and fixed 150 bugs, resulting in bug-free final silicon!
X-FAB
Melanie Wilhelm
X-FAB

Watch this 2-minute video to hear Melanie Wilhelm, a design engineer at X-FAB Semiconductor, a pure-play analog/mixed signal foundry, explain how the company revamped its low-power design flow using CPF to enable its customers to implement low-power functionality. Previously, X-FAB's flow resulted in users manually modeling the impact of low power during simulation. With a flow based on CPF and developed with Cadence's support, designers get a unified, continuous workflow to implement low-power functionality, along with better quality of verification and validation.
GLOBALFOUNDRIES
Ralf Flemming
GLOBALFOUNDRIES

SoC designs for the mobile market obviously need to meet stringent performance and power consumption targets. In this video, Ralf Flemming, a design engineer at GLOBALFOUNDRIES, explains how the company used a Cadence® low-power digital design and signoff flow to lower leakage power to 1.5% with 2GHz maximum frequency in its ARM® Cortex®-A17 processor-based family of SoC reference designs.
Hitachi
Toru Hiyama
Hitachi

In this 2-minute video, Hitachi's Toru Hiyama, general manager, Global MONOZUKURI Division, explains how using Cadence® high-speed verification tools, including the Protium™ and Palladium® XP platforms, helps the company achieve faster bring up and overall shorter time to market of its embedded software systems.
SiriusXM
Daniel Morera
SiriusXM

At SiriusXM, engineers develop satellite radio baseband devices that use higher density and higher frequency DDR3 memory. The company's latest design more than doubled the density and clock rate of previous designs. In this 3-minute video, hear Daniel Morera, a hardware engineer at SiriusXM, highlight the benefits the company gained by using Cadence® Sigrity™ tools to simulate and optimize the DDR3 interface before releasing their boards.
ams
Bertram Winter
ams

At ams AG, the engineering team had been performing electromigration checks at signoff. As a result, problems were detected late in the cycle, so the team had to make additional efforts to fix these problems. This was a costly approach that could potentially delay the project. Watch this short Expert Insights video to hear Bertram Winter, a design support engineer at ams, explain how Cadence's electrically aware design flow helped the team revamp its process to avoid additional design iterations.
 
Next »