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Freescale Semiconductor
Abhinav Nawal
Freescale Semiconductor

Watch this 3-minute video to learn how Freescale verifies its next-gen low-power SoC with Cadence® power-aware x-optimism simulation. Abhinav Nawal, a member of the company's SoC verification team, walks you through the process.
Cavium
Bill Munroe
Cavium

Routing boards with high-speed interfaces had been a time-consuming, manual process at Cavium. To alleviate scheduling pressures without sacrificing quality of their multi-layer boards, the San Jose, CA, semiconductor company automated the process with the Cadence® Allegro® TimingVision environment. In this 3-minute video, Bill Munroe, principal PCB designer in the company's Post-Silicon Group, talks about how the technology helped his team achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems.
Freescale Semiconductor
Sorabh Sachdeva
Freescale Semiconductor

Watch this 2-minute video to hear Sorabh Sachdeva, a design engineer at Freescale Semiconductor, explain how he and his team used Cadence® Virtuoso® Schematic Editor to solve their verification challenges on their mixed-signal, low-power, multi-voltage SoCs.
Tejas Networks
Amba Prasad
Tejas Networks

In this short video, Amba Prasad, product architect, R&D, at Tejas Networks, explains how the IPC-2581 design data format and Cadence® Allegro® tools eliminate surprises at the final stages of PCB design. These technologies are helping Tejas Networks deliver high-quality products faster than their competitors.
Analog Devices
Dushyant Juneja
Analog Devices

Functional verification is particularly challenging for mixed-signal SoCs. In this 3-minute video, Dushyant Juneja, a CAD engineer at Analog Devices, talks about early bug detection and more thorough functional verification of the company's mixed-signal and low-power designs. The company achieved this by applying advanced methodology based on real number modeling and simulation in Cadence® Incisive® Enterprise Simulator.
Freescale Semiconductor
Nikhil Murgai
Freescale Semiconductor

Routing and timing closure were big challenges on the high-performance cores developed by Freescale Semiconductor. How did the engineers improve these processes? Watch this video to hear Nikhil Murgai, lead design engineer at Freescale Semiconductor, talk about how the team used Cadence® Encounter® digital implementation tools to save routing resources and speed up the timing closure process.
ARM
Robert Kaye
ARM

Creating a virtual prototype becomes more challenging when graphics cores are involved because they have different instruction sets than CPUs. Watch this video to hear Robert Kaye, technical specialist with the Development Solutions Group at ARM, share tips and techniques for creating hybrid virtual platforms with the Cadence® Palladium® XP platform and accelerated verification IP.
National Instruments
George Zafiropoulos
National Instruments

From algorithms to pre- and post-silicon validation and test, the chip design process is supported by a variety of tools and methodologies. But, as you may well know, the process isn't always very efficient. In this 4-minute video, George Zafiropoulos, vice president of Solutions Marketing at National Instruments, talks about working with Cadence to develop a more efficient chip design flow. Hear what George has to say about what happens when a prototyping platform like Cadence's Palladium® environment is connected with National's test environment for full-chip validation.
Nexus Technology
Joe Socha
Nexus Technology

At Nexus Technology, Joe Socha, signal integrity engineer, is responsible for analyzing tiny PCBs that are used as interposers between memory devices and their target systems. Probing memory devices can be difficult, but an interposer allows the engineer to gain signal access. In devices such as DDR4 and LPDDR4, there are electrical and mechanical challenges that Nexus manages by using Cadence® Allegro® and Sigrity™ tools. In this video, Socha talks about how the Cadence Sigrity PowerSI® tool enables the team to run what-if cases to gain insights that lead to useful changes in trace widths, impedance, and more.
Allegro Microsystems
Khalid Chishti
Allegro Microsystems
 
In this Expert Insights video from CDNLive Boston 2014, Khalid Chishti, verification manager at Allegro Microsystems discusses how his automotive speed sensor mixed-signal IC project had many verification challenges causing inefficiencies and slowing time to market. They were able to get back on track with Cadence's Incisive® vManager™ solution, which provided a more powerful approach for combined digital and mixed signal verification, improving verification efficiency and productivity.
 
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