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Customer Success Videos 

Latest Success Videos
By Category  
Open-Silicon
Tilak Miryala
Open-Silicon

Open-Silicon develops complex chips with millions of gates, thousands of clocks, as well as repeatable blocks. Timing signoff and constraints validation can be quite challenging. Tilak Miryala, a design engineer at the company, talks about the limitations of a traditional ECO flow, the advantages of a traditional physically aware ECO flow, and, finally, the benefits of an MC-ECO flow available in the Cadence® Encounter® Digital Implementation System and Tempus™ Timing Signoff Solution.
MegaChips
Designing a networking chip with a hierarchical design can be very challenging in terms of timing correlation between synthesis and implementation and congestion after scan insert. Raghavendra Prasad, a senior design engineer at MegaChips, talks about how much measurable improvement the company gained by applying physically aware synthesis with Cadence® Encounter® RTL Compiler with Physical. Watch the video to learn how to avoid surprises in layout.
PMC
Using a traditional FPGA-based prototyping solution, PMC experienced system bring-up times that lasted from a week to two months. To speed up the process, while also using their existing Cadence® Palladium® XP environment, PMC migrated to the Cadence Rapid Prototyping Platform. Now, they can bring up a system in as little as a week and a half. Yogendra Pal, technical manager for product verification, and Ramchandra Vibhute, a staff engineer, tell you how in this 3-minute video.
ams
Thomas Moerth
ams

Engineers at ams AG were frustrated at how long it was taking to verify their mixed-signal designs. If there wasn't enough time in the schedule, the trade-off was to not verify everything, but risk having chips that didn't work as expected. Knowing that they had reached their limits with the hardware, the ams team turned to software for an answer. In this short video, Thomas Moerth, the company's manager of Design Support, Full-Service Foundry, talks about how Cadence® Virtuoso® AMS Designer helped ams complete 2X the number of simulations as was previously possible and how Cadence Spectre® Extensive Partitioning Simulator helped boost simulation speed by 10X.
STMicroelectronics
Samuele Raffaelli
STMicroelectronics

Samuele Raffaelli, a digital designer at STMicroelectronics, talks about how he and his team used, as a first step in verification, a formal verification methodology based on Cadence's Incisive® Formal Verifier and Incisive Enterprise Verifier for "exhaustive verification of the RTL." Watch the video to learn how the team reduced its verification time from 12 to 8 weeks.
Test and Verification Solutions
Mike Bartley
Test and Verification Solutions

What do you do when you've got an SoC verification project involving a testbench with a mix of different languages? In this 1.5-minute clip, Mike Bartley, CEO of Test and Verification Solutions, talks about how using open-source UVM-ML has allowed his team to reuse its legacy multi-language verification environment in a new UVM testbench environment. The team was able to wrap its Cadence® Incisive® Enterprise Specman Elite® Testbench in a UVM framework.
Dialog Semiconductor
Steven Holloway
Dialog Semiconductor

In this video from CDNLive EMEA 2014, Steven Holloway, Principal Verification Engineer of Dialog Semiconductor, discusses how he needed to successfully verify the register map in his parametric projects, while working around complex access policies, rapidly changing specifications, and the need to complete verification in an overnight regression run. Using Cadence's RegVal formal app flow, Holloway was able to automatically generate properties based on specifications, allowing him to run a validation regression on all 900 registers on the chip in six hours of CPU time and quickly debug any problems, all with less set-up time than it would take to put together a test bench.
Methods2Business
Marleen Boonen
Methods2Business

In this video from CDNLive EMEA 2014, Marleen Boonen, CEO and Founder of Methods2Business, discusses the company's need to build MAC layers for Wi-Fi 802.11n standards to get to market quickly without compromising on verification. Using the Cadence® C-to-Silicon Compiler's High-Level Synthesis Technology and Unified SystemC Modeling Methodology for high-level synthesis, virtual prototyping, and all verification, Methods2Business built not just working IP, but a MAC layer that is highly customizable in terms of power, performance, area, and functionality.
Test and Verification Solutions
Mike Bartley
Test and Verification Solutions

An SoC developer needed to speed up the time for verifying the DDR memory controller in its SoC. Mike Bartley, CEO of Test and Verification Solutions, found a faster way to do this by building a testbench with Denali™ memory models and using automated testbench generation via Cadence's Incisive® Enterprise Specman Elite® Testbench. Watch this 3-minute video to hear Mike explain how these tools helped save 50% of the effort on the 4-month project.
Freescale Semiconductor
Amitesh Khandelwal
Freescale Semiconductor

In this video, Amitesh Khandelwal, a Freescale Semiconductor design manager working on verification and validation domains, talks about the different challenges his organization faces in its SoC environments, from the lack of synergy and reuse to gaps in coverage in its test cases. With the Palladium XP platform, Freescale has gained critical coverage of the gap as well as a solution to quickly find critical bugs.
 
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