Freescale Semiconductor | Anis Jarrar
Freescale Semiconductor
Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC. |  |
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Silicon Blue Technologies | Andrew Chan
Silicon Blue Technologies
Andy Chan, Vice President of Engineering at Silicon Blue Technologies details how they utilize the TSMC-certified Cadence DFM Services along with Cadence technologies to develop consumer mobile applications |  |
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Xilinx | Larry Getman
Xilinx
Larry Getman, Vice President Processing Platform Marketing at Xilinx describes working with Cadence and the Virtual System Platform to developed the Zynq-7000, the industry's first virtual platform for system design and software development. |  |
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BIOTRONIK | David Genzer
BIOTRONIK
David Genzer, Director of IC Development at BIOTRONIK describes how they leveraged the Cadence digital implementation and signoff flow and CPF-enabled low-power solution to help deliver the most advanced and sophisticated pacemaker product on the market. |  |
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Ambarella | Chris Day
Ambarella
Chris Day, VP Marketing and Business Development at Ambarella, details the collaboration between Cadence and Samsung that resulted in a first-time silicon successful 32nm HD digital camera SoC. |  |
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Global Unichip Corporation (GUC) | Alex Kuo
Global Unichip Corporation (GUC)
Alex Kou, Senior Design Manager at Global Unichip Corporation, highlights how the CPF enabled Cadence Low Power Solution helps them achieve 100+ low power design tape-outs and address their low power design challenges in future technology nodes. |  |
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Samsung | Ana Hunter
Samsung
Ana Hunter, Vice President of Foundry North America at Samsung describes how they use Cadence technology to address challenges at 20nm technology node.
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Bosch | Peter van Staa
Bosch
Peter van Staa, Vice President of Engineering at Bosch highlights how they improved design efficiency by 25% utilizing the Cadence Design Environment. |  |
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Fujitsu Semiconductor Europe GmbH | Raimund Soenning
Fujitsu Semiconductor Europe GmbH
Raimund Soenning, Manager at Fujitsu Semiconductor Europe GmbH describes how they leverage the Cadence functional verification methodology to help develop large SoCs in the automotive industry. |  |
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austriamicrosystems | Thomas Riener
austriamicrosystems
Thomas Riener, Sr. VP, General Manager Foundry Business at austriamicrosystems describes how they leverage the Cadence unified custom/analog flow to design the company’s analog IC products. |  |
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