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Latest Success Videos |
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Broadcom | Vahid Ordoubadian
Broadcom
Vahid Ordoubadian, Director - Mobile Platform Group at Broadcom, describes the use of Cadence Palladium XP to validate a new architecture for a complex mobile SoC for mobile platform devices. |  | | ARM, Samsung and Cadence | ARM, Samsung and Cadence
Dipesh Patel, EVP and GM, Physical IP Division at ARM, Ana Hunter, VP of Foundry at Samsung Semiconductor and Chi-Ping Hsu, SVP, R&D at Cadence discuss the collaboration between the three companies to develop the first 14nm, FinFET implementation of the ARM Cortex A7. |  | | Analog Devices | Rohit Pandharipande
Analog Devices
Rohit Pandharipande, Design Engineer at Analog Devices, details working with Cadence migrating from VMM to the UVM Compliant, Cadence Verification IP (VIP) to verify a Dynamic Memory Controller. |  | | Open-Silicon, Inc. | Kavitha Nagarajan
Open-Silicon, Inc.
Kavitha Nagarajan, Lead Engineer – IC Package Design at Open-Silicon, Inc., describes how the company leveraged the Cadence Integrated SPB environment to successfully complete a complex project with a tight deadline. |  | | Open-Silicon, Inc. | Shrikrishna Mehetre and Souvik Mazmunder
Open-Silicon, Inc.
Hear from Shrikrishna Mehetre and Souvik Mazmunder, with Open-Silicon, Inc., as they highlight the use of Cadence Encounter digital RTL-to-signoff products to achieve 2.2 GHz performance on a 28nm ARM Dual-Core Cortex-A9 processor. |  | | STMicroelectronics | Abhishek Jain
STMicroelectronics
Abhishek Jain, Technical Manager at STMicroelectronics, talks about working with the Cadence Incisive Verification Solution to deploy a UVM multi-language, low-power verification methodology resulting in earlier and integrated verification. |  | | imec | Antoine Dejonghe
Program Manager
imec
Antoine Dejonghe, Green Radio Program Manager at imec, highlights the use of the Cadence CPF-Driven Advanced Low-Power Solution that accelerates the company’s next generation 4G wireless designs.
|  | | Duolog | David Murray
Duolog
David Murray, CTO at Duolog, discusses collaborating with Cadence to help customers address SoC integration and verification. |  | | Saphyrion |
Angelo Consoli
Saphyrion
Angelo Consoli, Managing Director at Saphyrion, details how they leverage the Cadence Virtuoso custom/analog flow and design services to develop ASICs High-End ground and space applications. |  | | Methods2Business | Marleen Boonen and Vladislav Palfi
Methods2Business
Listen to Marleen Boonen and Vladislav Palfi, from Methods2Business, as they describe how they use the Cadence Virtual Platform and Verum’s Analytical Software Design solution tool to debug earlier in the design cycle and ultimately design software faster and more efficiently. |  | | | | Next » |
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