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Latest Success Stories
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Business Challenges
  • Enhance ability to meet aggressive deadlines for particle physics research projects
Design Challenges
  • Automate aspects of FPGA board design, including pin placement and routing schemes
  • Quickly select the optimal FPGA package and pin count for the design
  • Quickly determine the right FPGA configuration and component setup for the design
Cadence Solutions
  • Allegro® FPGA System Planner
  • Allegro Design Authoring
  • Allegro PCB Designer
  • Allegro PCB SI
  • Saved one to two months on manual FPGA design-in effort for initial design
  • Made late changes to the design easily and in hours vs. weeks
  • Reduced, from 10 to 2 hours, the time to assess impacts of pin assignment changes on the FPGA timing and on place and route
  • Saved one month of project time due to FPGA-PCB co-design development ability
  • Reduced design iterations and, as a result, costs
  • Saved an hour of FPGA compile and validation time (using the Altera FPGA tools) for every pin assignment effort
  • Saved time and reduced errors through automated updates of symbols and schematics
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Business Challenges
  • Deliver product on time
  • Build customer confidence in a new and complex IP product
  • Mitigate risks of field failures
Design Challenges
  • Provide comprehensive breadth and depth test coverage in a massive verification space
  • Provide excellent debug tools and the ability to reproduce problems for rapid resolution of complex failure scenarios
Cadence Solutions
  • Palladium® XP series with simulation acceleration and emulation
  • Incisive® Enterprise Simulator
  • Increased validation speed hundreds of times faster compared to simulation
  • Enabled exhaustive test coverage of a massive verification space
  • Improved validation team productivity: operations that previously took weeks were completed in minutes
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  • High levels of signal processing and careful design to minimize power consumption and maximize performance for advanced LTE technologies
  • High costs related to IP licensing of different SoC components, tapeouts in advanced process geometries, carrier certifications and software investments
  • Aggressive time to market and price targets for chipsets
Cadence Solutions
  • Complete suite of analog IP
  • Analog design and integration expertise
  • Controller and PHY IP for LPDDR2, USB 2.0 ,and M-PCIe™ interfaces
Lessons Learned
  • Designing with Cadence silicon-proven analog IP is the best solution to reduce cost, accelerate time to market
  • Always work upfront with the IP vendor on AFE definition
  • Ability to compete in the rapidly growing LTE market space
  • Up to eight months faster time to market
  • Leading-edge products at a lower cost in terms of time, engineering, and tapeout
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Tait Communications
Business Challenges
  • Shorten library creation process
  • Make it easier and faster to locate parts
  • Maximize library management resource utilization
Cadence Solutions
  • Allegro® Design Workbench
  • Allegro PCB Library Workbench
  • Allegro PCB Editor
Lessons Learned
  • Implement automated library management via a phased approach
  • Synchronize Allegro PCB Library Workbench with an ERP system for timely, accurate parts data
  • 25% faster library creation process
  • 25% more schematic capture productivity
  • 10% more PCB design layout productivity
  • 40% less time spent managing parts libraries
  • 15% reduction in duplicated part library effort
  • 20% improvement in library model accuracy
  • More agile regulatory compliance process
  • Access to more up-to-date, accurate parts data
  • Faster, more efficient process to install software updates across the user base
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  • Needed robust, reliable IP to support MIPI SLIMbus audio bridge product
Cadence Solution
  • MIPI SLIMbus Manager Controller IP (with customizations including FTDI controller and I2S interfaces)
Lessons Learned
  • Developed own test tool for SLIMbus IP in order to remain independent from any IP vendor
  • More than 50% faster time to market for SLIMbus audio bridge product
  • LnK’s customers can minimize risk when moving to silicon
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Freescale Semiconductor
Business Challenges
  • Improve efficiency of top-level verification of mixed-signal SoCs
  • Tap into expertise of digital and analog engineers for top-level verification
Cadence Solutions
  • Virtuoso Analog Design Environment
  • Virtuoso AMS Designer Simulator
  • SimVision Debug
  • Incisive vManager solution
Lessons Learned
  • To ensure backwards compatibility to the legacy directed-test environment, use compiler directives to constrain random stimulus
  • When using a coverage- or metric-driven approach, simulation throughput is crucial, so it’s important to collect enough metrics
  • Orders-of-magnitude faster top-level verification of mixed-signal SoCs using wreal configurations
  • 2X more verification productivity for digital and analog engineers achieved through rapid simulation launch and re-invoke
  • Better coverage and traceability with Incisive vManager solution
  • Better bug detection using behavior wreal models verified against actual schematics
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Key Challenges
  • Achieve high performance of computing systems
  • Accelerate verification of high-performance computing systems
  • Better understand module behavior at the system level
Cadence Solution
  • Palladium® XP verification computing platform
Lessons Learned
  • Automatically generate assertions, via module level verification, to find overlooked behaviors
  • Caught 1/3 of system bugs
  • More than 150% faster overall verification process and savings of more than one re-spin
  • At least 300% faster post-silicon bring-up
  • 600% better engineering productivity
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Business Challenges
  • Automate PCB design routing for faster time to market
  • Continually enhance quality of PCB designs
  • Identify more detailed design constraints
Cadence Solutions
  • Allegro PCB Router
  • Allegro PCB Designer
  • OrCAD Capture CIS
Lessons Learned
  • Spend more upfront time capturing design intent
  • Have design constraints in place before placing the board
  • 10% faster time to market for boards, with 25% faster PCB design cycle
  • $50K saved annually through greater layout design efficiencies, which eliminates need to hire outside layout staff during busy cycles
  • Ability to perform “what if” analysis, resulting in better quality boards
  • Achieving higher quality avoids the tens of thousands of dollars that could be spent in the event of a respin
  • Better alignment between industrial and mechanical design phases contributes to better product quality
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  • Address increasing schedule pressures for complex, high-speed evaluation boards
  • Accelerate timing closure process while maintaining high quality of boards
  • Take on more projects with current staffing level
Cadence Solutions
  • Allegro® TimingVision™ environment
  • Allegro PCB Designer
  • Allegro PCB Router (previously known as SPECCTRA®)
Lessons Learned
  • Route DDR4 signals spaced at 5X the line width for better noise/coupling immunity
  • Ensure that differential pairs (static and dynamic phases) are all matched before trying to match lengths for all signals in a byte lane
  • Use application modes within Allegro PCB Designer to further increase tuning efficiency
  • Take advantage of user-redefinable, application-mode-sensitive “funckeys” to further shorten overall tuning proces
  • 4X faster timing closure, without compromise on quality
  • Ability to take on increased volume of PCB designs with existing resources
  • Faster “what-if” analysis with fewer layers for boards for routing DDRx interfaces
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ST Microelectronics
Business Challenge
  • Get automotive semiconductor products to market quickly, while adapting to frequently changing customer specifications
Design Challenge
  • Automate RTL ECOs for pre- and post-mask layouts
Cadence Solution
  • Encounter Conformal ECO Designer
  • 4 months average estimated savings in product development time
  • Significant mask-cost savings per design
  • Up to 30% productivity gain for design engineers
 Read full story»
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