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Customer Success 
Latest Success Stories
By Category  
LSI Corporation
Business Challenges
Establish a proven mixed-signal methodology to verify analog IP for a mixed-signal chip
Produce a high-quality product in a short time-to-market window
Design Challenges
Upgrade ad-hoc, manual verification methodology for analog IP
Leverage current, optimal verification flow for digital IP
Cadence Solutions
Incisive Enterprise Simulator
Incisive Enterprise Manager
Incisive Enterprise Specman Elite Testbench
Virtuoso AMS Designer
Virtuoso Schematic Editor
Virtuoso Analog Design Environment
Customer Support
Results
Established a methodology that can be extended to analog verification
Expanded analog design verification coverage and improved product quality
Met design and performance specifications
 Read Full story»
TowerJazz
Business Challenges
Time-to-market pressures
Rising development costs
Design Challenge
Product differentiation and customization for analog and mixed-signal specialty products
Cadence Solutions
Virtuoso unified custom/analog flow
Virtuoso Layout Suite
Virtuoso Analog Design Environment
Virtuoso AMS Designer
Virtuoso Spectre Circuit Simulator
Virtuoso Space-Based Router
Cadence QRC Extraction
Cadence Services
Results
Complete, customized offerings with a wide array of tools and functions
Lower development costs
Faster time to market
 Read Full story»
Technical University of Braunschweig
Challenges
Prepare students for workforce by teaching with powerful electronic design automation (EDA) technologies
Cultivate relationships with educators and corporations to further academic research in low-power digital design
Cadence Solutions
Cadence Academic Network
Incisive Unified Simulator
Encounter RTL Compiler
Encounter Digital Implementation System
3D Design Viewer
C-to-Silicon Compiler
Results
Students earn internships and jobs at leading technology companies with a strong presence in Europe
TUBS participates in publicly funded research projects involving low-power digital design
 Read Full story»
IBM
Business Challenges
Increasingly stringent specifications
Increasing complexity of sub-micron technologys
Design Challenges
Generate a robust model qualification flow for IBM SOI process nodes
Achieve first-pass design success with high correlations between silicon and circuit verification using advanced SPICE models
Cadence Solutions
Cadence Virtuoso Spectre Circuit Simulator
Cadence Virtuoso Multi-Mode Simulation
Results
Reduced overall SOI model validation cycle time for new compact model code by up to 30 percent
Improved productivity and SOI process node accuracy
 Read Full story»
Kilopass Technology
Design Challenge
Boost layout productivity
Improve communication between designers and implementation engineers
Quickly migrate from one process node for a given foundry to the next generation using a standard CMOS process

Cadence Solution
Virtuoso unified custom/analog flow (6.1)
OpenAccess database
 Read Full story»
VeriSilicon
Design Challenges
Accelerate the design process with automated, placement-aware pin assignment
Optimize the physical connectivity, even as it changes
Ensure quality and reduce complexity with reuse of interface rules and protocols

Cadence Solution
Allegro FPGA System Planner XL
 Read Full story»
JDSU
Design Challenge
Pin assignment for multiple FPGAs on a new optical network tester board
High-density, multi-port design with 5,500 components and stringent communications requirements
4,596 high-speed nets with constraints

Cadence Solution
Cadence Allegro FPGA System Planner
Cadence Allegro Global Route Environment
 Read Full story»
Siemens
Design Challenge
Build an all-encompassing chip-level verification plan over the entire functionality of the ASIC, including both hardware and software, that addresses real-life use cases and user scenarios
Reduce overall project time
Develop a flexible, trustworthy verification plan to stay on track, manage progress, and automate coverage collection to address unforeseen design changes
Integrate formal analysis technology into the verification flow

Cadence Solution
Cadence Incisive Enterprise Manager
Cadence Incisive Enterprise Specman Elite Testbench
Cadence Incisive Formal Verifier
Cadence Incisive Enterprise Simulator
 Read Full story»
Teledyne
Design Challenge
Performing metal-only ECO changes on derivative products had grown time-consuming and cost-prohibitive
Imager chip project scope included ECO modifications to eight different functional blocks—which could not be supported with existing manual ECO flow
Engineering team had concerns about maintaining quality while meeting project’s stringent timeline requirements

Cadence Solution
Cadence Encounter Conformal ECO Designer
 Read Full story»
Sigma
Design Challenge
Accelerate verification schedules and provide firmware engineers with earlier access to a hardware platform to verify their designs in a pre-silicon environment
Establish a methodology that can be easily integrated into existing processes

Cadence Solution
Palladium series of hardware assisted verification technologies with both in-circuit emulation and transaction-based acceleration capabilities
 Read Full story»
 
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