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Mixed-Signal Methodology Guide
This book, the Mixed-signal Methodology Guide: Advanced Methodology for AMS IP and SoC Design, Verification, and Implementation provides a broad overview of the design, verification and implementation methodologies required for today’s mixed-signal designs. The book covers mixed-signal design trends and challenges, abstraction of analog function using behavioral models, assertion-based metric-driven verification methodology and verification of low power intent in mixed-signal designs. It also describes methodology for physical implementation in context of concurrent mixed-signal design and for handling advanced node physical effects. The book contains many practical examples of models and techniques. The authors believe it should serve as a reference to many analog, digital and mixed-signal designers, verification, physical implementation engineers and managers in their pursuit of information for a better methodology required to address the challenges of modern mixed-signal designs.
Advanced Verification Topics
The Universal Verification Methodology (UVM) standard from Accellera is architected to scale with the growing digital design and across to the specialized verification needed for the new functionality. In addition, it naturally fits with the Metric Driven Verification (MDV) methodology that unifies the verification of the new functionality into a coherent verification plan. This book is for verification engineers familiar with the UVM and the benefits it brings to digital verification but who also need to tackle specialized tasks. It is also written for the SoC project manager that is tasked with building an efficient worldwide team. While the task continues to become more complex, UVM Advanced Topics provides the means to stay productive and profitable.
TLM-Driven Design and Verification Methodology Book
System level design concepts and automation are evolving at a fast pace. The recent emergence of high level synthesis has reinvigorated the use of SystemC for modeling designs and provided new opportunities to speed functional verification. Adopting these advanced technologies can be challenging from a learning perspective, and to optimize the results of the design, as well as schedule and cost of deployment. Methodology is a key to planning a strategy for adoption, and this book provides the first unified methodology considering high level synthesis and functional verification. It contains effective strategies and technical examples that ease absorption of complexities of system level design.

NEW! Japanese translation created with Professor Saito at Aizu University in Japan. TLM-driven Design and Verification Methodology book now in use in Graduate courses at Columbia and Aizu Universities.

NEW! TLM book now in Japanese! Get your copy today »
A Practical Guide to Adopting the Universal Verification Methodology (UVM) Book
The Universal Verification Methodology (UVM) is an emerging standard being developed by Accellera. It is based on a simple script conversion of the Open Verification Methodology (OVM) 2.1.1 and thereby inherits the quality and experience of ten years and thousands of successful verification projects. A Practical Guide to Adopting the Universal Verification Methodology, by Sharon Rosenberg and Kathleen Meade provides both, cookbook-style examples for novices and in-depth verification information including system-level verification, sequences for layered protocols, and register package use for expert verification engineers. The book also includes information on using transaction level modeling to interface SystemVerilog, e, and SystemC components together into a cohesive verification environment.
Co-verification of Hardware and Software for ARM SoC Design (Embedded Technology) Book
This book is the first to document and teach important information about the verification technique known as Hardware/Software Co-Verification. Traditional embedded system design has evolved into single chip designs that are pushing past 1M logic gates and headed toward 10M gates. In this era of SoC design, chips now include microprocessors and require software to be developed before hardware fabrication. To effectively develop quality products in a timely manner engineers must be armed with necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and assembly language embedded software. Individual books exist in each area, but until now the relevant information and how it all fits together has not been available. The book provides unique, in depth information about how co-verification really works, how to be successful using it, and the pitfalls to avoid.