Oki Tapes Out with New Cadence Synthesis Low-power TechnologyEncounter RTL Compiler Leverages Single-Pass Global Synthesis for 45% Power Reduction; 12% Area ReductionSan Jose, CA, 20 Dec 2004
Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN) today announced that Oki Electric Industry Co., Ltd. has successfully taped out a chip for Oki's µPLAT SoC design platform with the new low-power capability of Cadence® Encounter RTL Compiler synthesis. With Encounter RTL Compiler, Oki reduced power by 45 percent and area by 12 percent.
Designed to boost quality of silicon (QoS), Encounter RTL Compiler now addresses low-power implementation in a fundamentally new way by extending its multi-objective global optimization to dynamic and leakage power optimization. This single-pass solution offers improved power, timing and area for higher QoS. Encounter RTL Compiler's full low-power synthesis solution is unique in its simultaneous optimization of multiple objectives, yielding a faster route to silicon.
"At Oki, we are using Encounter RTL Compiler for our most important designs, based on our µPLAT System LSI Design Platform," said Shinji Furuno, a Senior Manager of Silicon Platform Design Department, LSI Design Division at Oki. "Encounter RTL Compiler's global synthesis enabled us to substantially reduce power and area, while producing a netlist that sped us through place and route more cleanly than we had experienced with previous technologies."
Power is a big concern for engineers working on nanometer-scale designs and has become the primary optimization objective in many projects. In the digital implementation flow, most of the leakage power optimization gains are made in the RTL to gate-level synthesis process. Encounter RTL Compiler's unique, single-pass approach to power, speed and area means higher QoS and a simplified design flow. QoS measures a design's physical characteristics using wires in terms of improved area utilization, higher performance and lower power consumption. Through this, trial and error through multiple runs and multiple tools is substantially reduced.
"We are pleased that such an important customer as Oki has greatly enhanced its low-power design capability with Encounter RTL Compiler," said Chi-Ping Hsu, corporate vice president at Cadence. "With our new global synthesis technology, Cadence delivered improved QoS with faster runtime and higher capacity. This leveraged the advantages of Oki's µPLAT integration platform and design environment for improved SoC quality."
Encounter RTL Compiler includes a unique set of global focus algorithms to maximize the performance of today's most challenging low-power designs. It works with existing design flows to increase chip performance, decrease design times, and provide the highest QoS.
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Cadence is the world's largest supplier of electronic design technologies and engineering services. Cadence products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics based products. With approximately 4,850 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and trades on both the New York Stock Exchange and Nasdaq under the symbol CDN. More information is available at www.cadence.com