will be under system maintenance from Tuesday June 28, 6pm PT to Sunday July 3, 11pm PT. Login and registration will be disabled.


Faraday Successfully Completes a Range of 130-nm Tapeouts with Cadence Encounter
Cadence Synthesis and Physical Implementation Flow Continues to Help Faraday Achieve Low-Power Requirements

Hsinchu, Taiwan and San Jose, Calif, 19 Dec 2005

Faraday Technology Corporation (TAIEX: 3035) and Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Faraday has successfully taped out ten 130-nanometer ASIC production chips with the Cadence® Encounter® digital IC design platform. Ten other 130-nanometer ASIC chips are currently being designed at Faraday using the Encounter platform.

The 130-nanometer Faraday chips, with gate counts from 2 million to 5 million, are designed for a wide range of applications such as high-performance networking (450MHz), low-power mobile video, and portable PC peripherals. The Cadence Encounter platform provided extensive timing/signal integrity (SI) closure and low-power features, which enabled Faraday to quickly implement low-power structured as well as standard cell ASICs. Additionally, Faraday improved the competitiveness of its silicon intellectual property (IP) by using Encounter RTL Compiler global synthesis.

"We have successfully taped out ten 130-nanometer customer chips using the Encounter platform," said Victor Lin, vice president of ASIC Technology at Faraday. "With Cadence’s help we are able to achieve smaller die sizes, higher performance, and lower power, which are exactly what customers expected."

The Encounter digital IC design platform provides a complete RTL-GDSII implementation solution. It includes Encounter RTL Compiler global synthesis technology for low-power-aware logic and physical synthesis, Encounter NanoRoute™ nanometer routing, and signoff-quality SI- and IR-aware timing with Encounter CeltIC™ and VoltageStorm analysis.

"We are pleased that Cadence Encounter products for synthesis, signal-integrity-based timing closure and low power have contributed to Faraday’s success in a wide variety of markets, including IP, ASIC and structured ASIC," said Wei-Jin Dai, vice president, digital IC implementation at Cadence. "We applaud Faraday's success in maximizing the benefits of Encounter."

About Faraday Technology Corporation
Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company’s broad IP portfolio includes 32-bit RISC CPUs, DSPs, and PHYs/Controllers for USB 2.0, Ethernet, Serial ATA and PCI Express. With more than 500 employees and 2004 revenues of US$159 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other worldwide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe and China. For more information, please visit:

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

For more information, please contact:
Michael Fournell
Cadence Design Systems, Inc.

Diana Wu
direct:+ (886)3-578-7888 ext8032
Faraday Technology Corporation

Cadence and the Cadence logo and Encounter are registered trademarks, NanoRoute and CeltIC are trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.