Inphi Tapes Out High-speed Flip-chip Design with Cadence Encounter Platform
Encounter Global Synthesis and Physical Implementation Help Inphi Corp. Achieve 666 MHz at 130-nm with Flip-Chip Package

SAN JOSE, Calif., 13 Dec 2005

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Inphi Corporation has successfully taped out a complex high-speed chip using the Cadence® Encounter® digital IC design platform, including Encounter RTL Compiler global synthesis and the SoC Encounter™ hierarchical RTL-to-GDSII system.

Inphi's design, for the ExacTik (TM) INAMB581 server memory chip, achieved its goal of 666 MHz with a TSMC 130-nanometer process. Physical implementation of this mixed-signal design had the added complexity of a 529-pin flip-chip package. Inphi is a privately held fabless electronic-components company with strengths in high-speed analog IC design and packaging for computing, communications and instrumentation systems.

Encounter RTL Compiler global synthesis helped Inphi meet its aggressive frequency target by reducing synthesis turnaround times, which enabled more experimentation with its powerful global optimizations. Then Inphi used Encounter's skew capabilities to close timing in physical implementation. Inphi also used the First Encounter® silicon virtual prototyping flip-chip router for automatic redistribution-layer (RDL) routing.

"Implementation of our chip was extremely challenging given the aggressive frequency target and the complexity of a mixed-signal design with a flip-chip package," said Gopal Raghavan, founder and chief technology officer at Inphi. "Encounter RTL Compiler global synthesis enabled us to meet our aggressive frequency target, and Encounter's automatic RDL routing for flip chips helped us meet our schedule. Altogether, the Encounter platform provided us with a powerful solution to help us meet our demanding goals."

Cadence's Encounter Digital IC design platform starts with Encounter RTL Compiler global synthesis, which delivers smaller, faster and cooler chips in less time. It is followed by the SoC Encounter hierarchical RTL-to-GDSII system, which delivers the fastest path to tapeout for large, complex ICs.

"We are excited that Encounter's global synthesis and physical implementation helped our customer achieve this aggressive frequency goal," said Dr. Chi-Ping Hsu, corporate vice president at Cadence. "We are rapidly advancing our technologies to help customers win in their competitive markets."

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Michael Fournell
direct:408-428-5135
fournell@cadence.com
Cadence Design Systems, Inc.


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