AppliedMicro Standardizes on Cadence Encounter Digital Implementation System
Cadence Enables Aggressive Leap from 90nm to 40nm Technology and Delivers Advantage in Low Power and Yield for Complex Hierarchical Design

SAN JOSE, Calif., 08 Dec 2009

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Applied Micro Circuits Corporation (NASDAQ: AMCC) has selected the Cadence® Encounter® Digital Implementation (EDI) System for its large, complex advanced-node designs. EDI System joins other multiprocessing-capable offerings in the AppliedMicro™ methodology to form a standardized design infrastructure based set of tools.

“The Cadence EDI System has fast and comprehensive floorplanning capabilities, advanced node-ready hierarchical design closure, low power and integrated yield optimization features. We achieved significant area reduction and higher utilizations on our toughest designs, which were unroutable using our previous methodology,” said Amal Bommireddy, vice president of engineering at AppliedMicro. “With our Encounter RTL Compiler global synthesis and Encounter Conformal technology adoption last year, and EDI System this year, we’re achieving greater productivity and faster time to market for our area-critical, high connectivity, advanced digital networking chips. Its innovative floorplan synthesis, multiprocessor enabled placement, partitioning, budgeting and advanced power planning techniques brought faster, easier hierarchical design closure.”

Cadence’s Nanoroute routing enabled AppliedMicro to port its design from a 90-nanometer process technology to 40 nanometers, while addressing advanced techniques such as multi-cut vias and litho-aware routing.

“Last year, AppliedMicro brought us in to evaluate our Encounter RTL Compiler and Conformal technologies, which were ideally suited for their needs,” said David Desharnais, group director of Implementation Product Management at Cadence. “This year, they decided to conduct a reevaluation of their entire design flow, to ensure that they were getting the most efficient and robust digital solution for their complex 40-nanometer designs. The selection of the Cadence EDI System rounds out AppliedMicro’s design methodology, joining the Cadence Virtuoso® custom IC solution and Cadence Allegro® PCB and packaging technology to enable world class design solution for AppliedMicro.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Dan Holden
Cadence Design Systems, Inc.
408-944-7457
holden@cadence.com


Cadence, the Cadence logo, Encounter, Allegro and Virtuoso are all registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. AppliedMicro is a trademark of Applied Micro Circuits Corporation. All other trademarks are the property of their respective owners.