P.A. Semi Develops 65nm, Multicore Processor Family Using Cadence Synthesis and Implementation
Encounter Digital IC Design Platform Supports Rapid Development of 64-Bit, High-Performance, Low-Power Power ArchitectureTM Based Design

SAN JOSE, Calif., 05 Dec 2005

Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced that the Cadence® Encounter® digital IC design platform has helped P.A. Semi develop its new 65-nanometer multicore PWRficient processor with a successful test-chip tapeout in March 2005. P.A. Semi's first PWRficient processor, a dual-core device operating at 2GHz with five- to 13-watt power dissipation, is being developed from the ground up using the complete Encounter solution from RTL synthesis to GDSII. Silicon samples of the test chip are running at 2GHz.

Based on the IBM Power Architecture, the scalable, power-efficient PWRficient platform-processor family targets the high-performance embedded and computing markets.

"The Cadence Encounter platform helped us achieve our test-chip tapeout and is assisting us in keeping our processor tapeout on schedule," said Sribalan Santhanam, vice president of engineering, Design Group, at P.A. Semi. "The SoC Encounter XL RTL to GDSII system's advanced capabilities in RTL global synthesis, floorplanning, global physical synthesis and routing helps our designs to meet the required performance specifications, and the NanoRoute™ nanometer router's ability to support 65-nanometer rules is unprecedented."

"IBM Power Architecture has excellent momentum in many markets including computing, gaming and embedded applications. Continued expansion into other markets requires active support from the design chain," said Tom Reeves, vice president of Semiconductor Products at IBM Systems & Technology Group. "We recognize this as a significant achievement by P.A. Semi in developing its first Power Architecture based processor using the Cadence Encounter platform."

To achieve the power, frequency, and density targets for the design, P.A. Semi tapped the strength of a complete SoC Encounter XL-based flow. This RTL-to-GDSII system includes RTL global synthesis, prototyping, placement, optimization, and routing. Advanced capabilities in multi-objective low-power synthesis, global physical synthesis, clock-tree synthesis, manufacturing-aware extraction, and signal integrity and power analysis specifically address the complex issues of 65-nanometer design.

"We are extremely happy to see P.A. Semi achieve its objectives using the SoC Encounter flow," said Wei-Jin Dai, corporate vice president, R&D for Cadence. "The SoC Encounter system's strength is support for these types of complex, high-performance designs. We are particularly proud to be a part of P.A. Semi's development of a 65-nanometer product."

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Judy Erkanat
direct:408.894.2302
jerkanat@cadence.com
Cadence Design Systems, Inc.


Cadence, the Cadence logo and Encounter are registered trademarks, and NanoRoute is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.