Sirific Wireless readies two 3.5G RF transceivers for market using Cadence Logic Design technologyEncounter RTL Compiler with Advanced Global Synthesis Technology Helps Sirific Speed Time to Market for HEDGE ChipsSAN JOSE, Calif., 27 Nov 2006
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced today that Sirific Wireless, the global leader in highly integrated, single-chip, multi-mode CMOS RF transceivers, has taped out and is approaching production of two 130-nanometer 3.5G multi-band HEDGE transceiver chips using the Cadence® Logic Design Team Solution. The Cadence technology includes Encounter® RTL Compiler XL with advanced global synthesis, Encounter Conformal® Equivalence Checker, Encounter Test, and Incisive® Design Team simulation.
Sirific Wireless is a fabless semiconductor company that designs and delivers single-chip multi-band radio solutions for multi-mode, HSDPA, WCDMA, EDGE, and GSM/GPRS applications that set new benchmarks for functionality, cost, component count, size and power consumption. Using the Cadence Logic Design Team Solution, Sirific was able to accelerate their time to market.
"Encounter RTL Compiler XL synthesis has been an invaluable tool in helping Sirific advance digital design in 130-nanometer CMOS by speeding the implementation of our Digital Direct Conversion receiver and Harmony transmitter, which both use the DigRF 2.5G baseband interface," said Mike Hogan, president and CEO of Sirific Wireless. "Overall, the Cadence Logic Design Team Solution provided our engineers a faster, easier-to-use method for synthesizing and verifying digital circuits across the NEXUS III family of products allowing us to quickly bring to market the world's first single-chip multi-band HEDGE RF transceiver."
The Cadence Logic Design Team Solution provides an innovative integrated environment that combines design, early verification and front-end implementation tasks. Encounter RTL Compiler synthesis has proven through tapeouts to deliver improved performance, smaller die sizes, lower power consumption, and faster design closure through place and route.
"We're excited that the Cadence Logic Design Team Solution assisted Sirific in integrating their advancements for increasing digital functionality in multi-band CMOS RF design," said Nimish Modi, corporate vice president of Front-end Design at Cadence. "Sirific's products exemplify Cadence's commitment to enabling semiconductor companies to advance the communications market."
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Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com