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ARM and Cadence Collaborate on Testability Requirements of ARM Partners with Encounter Test
Timing- and Power-Aware Encounter True-Time Test ATPG Detects Small Delay Defects While Managing Power During Test

SAN JOSE, Calif., 24 Oct 2006

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it is collaborating with ARM to expand the breadth of the joint ARM and Cadence® Encounter® Reference Methodology with the addition of Encounter Test timing and power-aware technology. The addition of True-Time Test ATPG will provide capabilities to develop tests that detect small delay defects while concurrently managing power consumption during test.

The ARM and Cadence Encounter Reference Methodology is a proven implementation flow that delivers a powerful, deterministic, and rapid route from RTL to GDSII for ARM synthesizable processors. This methodology increases the productivity of the design team and reduces time to silicon with predictable performance, power, and area results. In addition, by providing accurate abstract models, the methodology enables licensees to deploy the ARM processor as a library component for system-on-chip (SoC) integration by end users.

"The addition of Encounter Test to the Reference Methodology provides a high-value capability for design teams," said Keith Clarke, vice president of Technical Marketing at ARM. "Efficient detection of small delay defects, and management of power during test, are both important elements in getting the best results during development of ARM processor-based SoC."

"To handle all of the latest 3G wireless protocols, the Sandbridge SB3000® family of flexible baseband processors relies on an ARM 9 processor driving four Sandblaster® DSP cores in parallel. Design for test (DFT) and Automatic Test Pattern Generation (ATPG) are critical design steps toward ensuring that our chips can be tested rapidly and reliably post-manufacturing, and guarantee to our customers they will not run into any problems in the field," said Gary Nacer, vice president of Engineering at Sandbridge Technologies, Inc. "Encounter Test products thus play a critical role in our IC design flow. We believe an ARM reference design flow and methodology resulting from our collaboration with Cadence can significantly improve our productivity in future generations of SB3000 designs."

Cadence Encounter Test, a key component of the Cadence Encounter digital IC design platform, delivers the industry's most advanced test solution from RTL to silicon. Key technologies include power-aware ATPG methods to reduce power during test, test data compression to lower cost of test, True-Time delay test to detect small delay defects and enable the highest quality of shippable silicon, and Encounter Diagnostics to accelerate yield ramp.

"The inclusion of Encounter Test in the ARM and Cadence Encounter Reference Methodology is an important milestone not just for our partnership, but for the design community," said Sanjiv Taneja, vice president of R&D for Encounter Test at Cadence. "It provides the ARM user community with an important tool to ensure high quality electronic design. We look forward to future collaborations that advance the art of semiconductor test."

Encounter True-Time Test is available in L, XL and GXL configurations tailored to meet specific levels of testing complexity.

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Dan Holden
direct:408.944.7457
holden@cadence.com
Cadence Design Systems, Inc.


Cadence and Encounter are registered trademarks and, the Cadence logo is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

ARM is registered trademark of ARM Limited. ARM9 is a trademark of ARM Limited. All other brands or product names are the property of their respective holders. "ARM" is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.; AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Solutions Pvt. Ltd.; and ARM Physical IP, Inc.; and ARM Norway AS.