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Silicon & Software Systems Completes 65nm Consumer Chip with Cadence Encounter
Production 65 Nanometer RTL-to-GDS Design Flow Supports Rapid Development of 500MHz IC in Leading-Edge Nanometer Silicon Technology

SAN JOSE, Calif., 03 Oct 2005

Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN) today announced that the Cadence® Encounter® digital IC design platform has helped Silicon & Software Systems (S3) to successfully tape out a new production 65-nanometer design. The 500-MHz consumer computing device, designed under contract for a major European customer, will be manufactured in a leading European 65-nanometer silicon wafer fab and is expected to reach very high production volumes.

To help implement this and other 65-nanometer test-chip and sub-block designs, S3 leveraged the complete Encounter RTL-to-GDSII flow, and applied its proven methodologies and approaches to solve the complex challenges of nanometer process design. This included building an automated environment for 65-nanometer mixed-signal design flow with RTL synthesis, virtual prototyping, physical synthesis, routing, signal and power integrity analysis, and 3D extraction. This scripted design flow enabled fast design migration, regression turnaround time, rapid timing and signal integrity closure, high-speed digital, and mixed-signal routing to ensure high quality results in an evolving technology context.

"Moving from the 90- to the 65-nanometer node offered our customer significant advantages in die area and performance, and our advanced implementation flow helped control leakage power and other potential manufacturability challenges with the silicon," said Dermot Barry, general manager of the System IC Business Unit at S3. "The integrated Encounter RTL-to-GDSII flow allowed us to quickly and easily exercise multiple 'what-if' scenarios and revisions of our design as the library matured and new requirements were added. This allowed us to provide our customer with the best quality of silicon possible in the shortest amount of time. With this implementation flow, S3 is fully operational at the 65-nanometer node and we are taking new designs now."

S3 provides outsourcing solutions to semiconductor and system companies at the leading edge of system IC design. It provides a complete system IC capability from specification to tape-out and has an excellent first-time right track record.

"Building on its leadership position at 90 nanometers, S3 has clearly demonstrated its capability to migrate complex designs to the 65-nanometer technology node," said Wei-Jin Dai, corporate vice president, R&D for Cadence. "We continue to be impressed with the excellent engineering team at S3 and are proud that they have chosen Encounter as their standard leading-edge synthesis and implementation solution. Once again, Encounter is recognized as essential technology by an important customer."

S3's website is www.s3group.com.

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Judy Erkanat
direct:408.894.2302
jerkanat@cadence.com
Cadence Design Systems, Inc.


Cadence and the Cadence logo are registered trademarks and Encounter, SoC Encounter and NanoRoute are trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.