Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced that it has created a lithography-aware design flow and has defined an interface that will link resolution enhancement technologies (RET) with physical design and verification. Cadence has collaborated with Brion Technologies and Clear Shape Technologies in developing this flow which addresses critical lithography-induced yield problems and mask-design challenges.
Design teams can now use the same models throughout the flow across design, implementation and manufacturing, including combining automated layout optimization with advanced manufacturability models in design phases. The Cadence® interface will be used for the Cadence Encounter® digital IC design platform as well as third-party developed design-for-manufacturing (DFM) technologies.
"In keeping with our vision and plan to create a lithography-aware design and implementation flow targeted for challenges at 65 nanometers and below, we've defined an interface that links both internal and external lithography modeling and verification technologies with our design and implementation solutions," said Wei-Jin Dai, corporate vice president at Cadence. "This design flow is intended for customers who are designing at leading-edge 65-, 45-, and 32-nanometer processes and those developing lithography-aware DFM flows."
Clear Shape has developed DFM technologies for fast and accurate systematic, full-chip, model-based manufacturing shape analysis for both catastrophic and parametric issues. Brion Technologies has leveraged its computational lithography technology to deploy an accurate, fast, full-chip optical proximity correction (OPC) and OPC verification solution. By linking either company's technologies with the Cadence Encounter® digital IC design platform including Cadence Chip Optimizer using the newly defined interface, Cadence provides customers with an integrated lithography modeling, design implementation and layout optimization flow. The collaborations enable IDMs and fabless semiconductor companies to identify and eliminate lithography hot spots and to optimize both Manhattan and X designs for yield while retaining design and electrical intent.
"As we implement advanced process flows, we see lithography impacts on design becoming more and more critical," said Shuichi Inoue, general manager, Process Technology Division at NEC Electronics Corporation. "As a customer of both Brion and Cadence, we're pleased to see this type of collaboration, which enables a lithography-aware design flow that correlates well to the mask-making and manufacturing stages. NEC Electronics will help to drive and to provide requirements and directions for this effort."
"Cadence and Brion have collaborated for months to define a lithography-aware design flow that enables our mutual customers to link signoff quality OPC and OPC verification with design stage layout optimizations," said Dr. Shauh-Teh Juang, senior vice president of marketing and business development at Brion Technologies. "With 12 of the top 15 semiconductor manufacturers using Brion for OPC or OPC verification, we are seeing the demand for this type of design flow which minimizes the risk of costly yield issues."
"We are pleased to be a part of this collaboration with Cadence," said Atul Sharan, CEO of Clear Shape Technologies. "At sub-90nanometers the industry needs to move from ideal-GDSII based design to true silicon-accurate design. Clear Shape has developed unique technologies that enable fast and accurate prediction of silicon in an OPC & RET tool-agnostic manner. Our goal is to put DFM solutions that analyze and account for systematic variations on designers' desktops. Linking our technologies with Cadence's widely deployed physical design and verification platforms provide designers a plug-in solution that bridges design and manufacturing."
"The new lithography-aware design flow will allow ATI to link manufacturability and design implementation, providing an important element of our robust DFM strategy," said Greg Buchner, vice president, Engineering, ATI Technologies Inc. "By utilizing Cadence Chip Optimizer to automatically fix hot spots that are accurately predicted during our physical design phase by Clear Shape's InShape tool, we are able to prevent costly and time-consuming iterations that rely on detecting lithography problems after tape-out or, even worse, in silicon. We're encouraged by this type of collaboration and hope to see more situations of companies working together to help solve broader industry problems."
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
About Brion Technologies
Brion Technologies, Inc. is the pioneer and leader in Lithography-Driven Design & Manufacturing. Founded in 2002, the privately held company is headquartered in Santa Clara, California. Brion's Tachyon platform, a highly accurate and ultra-fast OPC and OPC verification engine, enables a unique set of capabilities that address the interrelated challenges of design, photomask making and wafer printing in semiconductor microlithography. With over 125 employees, the company leads the worldwide market for optical proximity correction (OPC) verification, and is rapidly expanding in the OPC market. For further information, visit Brion Technologies' Web site at www.brion.com or call +1 (408) 653-1500.
About Clear Shape
Clear Shape Technologies, Inc. is focused on providing leading edge design-for-manufacturing (DFM) solutions that detect catastrophic and parametric manufacturing failures during design, improve yield, and enable designers to control, manage and optimize the impact of systematic variation on chip performance, signal integrity, and leakage power. Clear Shape's product is in the DFM qualification program of TSMC, UMC and IBM-Chartered-Samsung. Clear Shape is backed by top-tier venture investors that include USVP, Intel Capital and KT Ventures (KLA Tencor). The company is headquartered at 3255-3 Scott Blvd, Suite 102 Santa Clara, Calif. 95054. For more information, visit www.clearshape.com
or call +1 (408) 833-7130.