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ITRI Tapes Out Low-Power DVFS Test Chip with Cadence Encounter Synthesis and Implementation
Encounter Low-Power Design Methodology Helps Slash Power Consumption Up To 40%

SAN JOSE, Calif., 08 Sep 2005

Cadence Design Systems, Inc. (NYSE: CDN) (Nasdaq: CDN) announced today that the SoC Technology Center (STC) of the Industrial Technology Research Institute (ITRI), Taiwan, has taped out a low-power test chip using the Cadence® Encounter® digital IC design platform and its RTL-GDSII low power methodology. STC worked on ITRI's Application-aware Power Management Solution Package -PAC-LP. This includes Dynamic Voltage Frequency Scaling (DVFS) design methodology, IPs for DVFS design (Level-Shifter, special, and DVFS controller), and Dynamic Power Management Software.

As proven on PAC-LP, one of today's most advanced low power techniques, the Encounter low power design flow can help with DVFS test chip design, especially with multi-VDD power domain floorplanning, automatic Level-Shifter insertion, and multi-VDD power domain place and route. The resulting test chip can reduce power consumption up to 40 percent.

With the support of multi-VDD methodology, the Encounter low power design flow further expands its comprehensive set of low power techniques applicable to wireless, communication, consumer, and computing applications. Encounter is proven to be the easiest and most effective solution for addressing the escalating power challenges in 90- and 65-nanometer cell-based digital designs.

"This chip tests the Application-aware Power Management Solution Package and the important functionality of a dual-core multi-media application processor SoC which we will be taping out early next year," said Dr. Chien-Wei Jen, the General Director of STC. "The support of multi-VDD methodology in implementing this chip represents a significant achievement by the Encounter multi-VDD low power design flow."

ITRI, a Taiwanese non-profit research and development organization, achieved tapeout in record time with significant savings in power consumption using Encounter's domain-aware design flow. The domain awareness starts at the synthesis stage and continues through implementation and verification. This includes Encounter RTL Compiler single-pass multi-objective synthesis, SoC Encounter™ global physical synthesis (GPS), a configuration of the Cadence Encounter digital IC design platform that combines RTL and physical synthesis, silicon virtual prototyping, and full chip implementation into a single system, and VoltageStorm® static and dynamic power analysis.

In addition to the DVFS flow's reduction of dynamic power consumption, the low voltage section of the design also showed less leakage power than the baseline flow implementation. This was delivered by Encounter's easy single-pass leakage optimization, which starts with global synthesis and continues through placement, optimization, and routing.

"ITRI's successful tapeout demonstrates the production readiness of Encounter's MSV methodology," said Wei-Jin Dai, platform vice president, digital IC implementation at Cadence. "DVFS methodology is one of the world's most advanced low power methodologies, and we are proud to be able to support its design and implementation."

With the mission of stimulating Taiwan's semiconductor industry to transform into a high value-added industry with innovative design, STC was established on March 1, 2003 as a formal research center in ITRI, a leading non-profit R&D organization. From the industrial perspectives, STC focuses on DSP Core, Multimedia SoC, Low Power Design Technology, RF/Mixed Signal IC, and IC Design and Test Service to provide the most advanced technologies to meet domestic and international product development needs. STC also aims to link up system applications and processing technology for implementing the integration of SoC design. For more information about STC and ITRI, please visit or

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

For more information, please contact:
Judy Erkanat
Cadence Design Systems, Inc.

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