Cadence Announces Industry’s First DDR4 Design IP Solutions Are Now Proven in 28nm SiliconCadence Design IP family for DDR4 Delivers High Performance and Low Power in TSMC 28HP and 28HPM SiliconSAN JOSE, Calif. , 04 Sep 2012
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that the first products in the Cadence DDR4 SDRAM PHY and memory controller design intellectual property (IP) family have been proven in silicon on TSMC’s 28HPM and 28HP process technologies.
Extending its leadership in advanced DRAM interface IP technology, Cadence has received and characterized multiple versions of its DDR PHY and controller IP in 28nm silicon based on advanced drafts of the DDR4 standard. The proposed DDR4 standard, anticipated to be released by JEDEC later this year, will offer users substantial performance benefits over DDR3. DRAM devices adopting the DDR4 standard are expected to have 50 percent higher operational frequency and double the memory capacity of DDR3 devices while reducing the power consumed in the DRAM by as much as 40 percent per bit transferred.
"DDR4 is going to be the next big thing in DRAMs, but its signaling is challenging to handle," said Jim Handy of Objective Analysis. "As PCs migrate to DDR4 DRAMs, this standard will become the volume leader, giving it a price advantage that will be impossible to ignore. ASIC designers who want to take advantage of that pricing are likely to need a lot of help putting a reliable interface on their products."
The Cadence silicon-proven PHY family includes a high-speed implementation of the DDR4 PHY that exceeds the data rates specified in the DDR-2400 draft, meeting the requirements of next-generation computing, networking, cloud infrastructure, and home entertainment devices, while offering interoperability with current DDR3 and DDR3L standards. Also proven in TSMC 28HPM silicon, is a low-power, all-digital mobile PHY implementation that exceeds the data rates called for in both the DDR-1600 and DDR-1866 DDR3 standards and the maximum data rate of the low-power LPDDR2 standard. As a result, SoC designers can now deploy fast, power-efficient memory technologies in next generation mobile designs with confidence.
“We are excited to be the first to offer silicon-proven DDR4 memory controller and PHY IP that will enable our customers to exceed performance and power requirements in their next generation SoCs with reduced risk,” said Marc Greenberg, director of product marketing, SoC Realization Group at Cadence. “Our broad portfolio of leading design IP solutions delivers advanced features, and a unique approach to customization that allow our customers to deliver highly differentiated products while shortening their time-to-market.”
All Cadence DDR Memory solutions mentioned herein are available today.
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Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.