Cadence Design Systems, Inc. (NASDAQ: CDNS) and Taiwan Semiconductor Manufacturing Company (NYSE: TSM) today announced the integration of the Cadence® Encounter® digital IC design platform and Cadence Allegro® system interconnect platform into TSMC's Reference Flow 7.0. With this reference flow, which supports designs targeting TSMC's Nexsys™ 65-nanometer, process technologies, Cadence continues an established track record of innovation by improving its software for power optimization and analysis, design for manufacturing (DFM), chip-package integration, and design for test (DFT).
This latest milestone in the ongoing collaboration between the two companies delivers an RTL-to-package reference flow to accelerate time to volume for high-performance designs and low-power designs. The flow delivers a comprehensive methodology to address complex design issues at 65 nanometers, such as tight manufacturing parameters, an exponential increase in leakage power, and new extraction requirements. Within Reference Flow 7.0, Cadence technologies address these key issues by improving concurrent routing and dual-via insertion, adding new leakage power reduction strategies, addressing process-variation extraction issues, and continuing to optimize package performance and cost. Also within Reference Flow 7.0, Cadence is for the first time providing a complete RTL-to-GDSII and package flow, including all past and present TSMC Reference Flow capabilities for optimal customer referenceability.
"We worked closely with Cadence to meet the complex requirements that designers are facing at 65 nanometers, challenges such as power management, chip and package co-design, and manufacturing," said Ed Wan, senior director of design service marketing at TSMC. "The Cadence track within TSMC's Reference Flow 7.0 incorporates their technologies to lower the entry barrier for designers targeting TSMC's advanced processes."
"Reference Flow 7.0 offers comprehensive solutions to a complex 65-nanometer design. Manufacturing variance and accurate modeling are crucial for silicon design success at that node. Cadence provides a complete and integrated solution in TSMC Reference Flow 7.0 from low-power implementation, timing analysis to DFM and SSTA," said Wei-Jin Dai, corporate vice president of Research and Development at Cadence. "The breadth of offerings and the capability to integrate into an easy-to-use flow is the key value that Cadence delivers to customers. Cadence also provides a 65LP tutorial and test case in the TSMC Reference Flow. Customers can download and walk through the complete flow with a real design."
Power Optimization and Analysis
TSMC Reference Flow 7.0 continues to leverage key elements of the Cadence Encounter platform from Reference Flow 6.0, including voltage domain-aware technologies used to create power-gated paths and dynamic-voltage scaling, as well as path-specific power optimization using fine grain multi-threshold transistors (MTCMOS). Reference Flow 7.0 expands the range of power optimization options to include both coarse grain MTCMOS power gating and dynamic-voltage and frequency scaling. Designers can use these technologies not only to design with multiple supply voltages and power domains, leakage power and de-coupling capacitance optimization, automatic power-grid generation, and dynamic voltage (IR) drop analysis with actual IC package load models, but also to employ multiple modes of operation within a single block. The Encounter platform provides a scalable methodology to go from a non-power domain design to power-domain-based designs, as well as to choose between many options to maximize power optimization with acceptable area and/or performance.
Complementing this range of power optimization choices, the Encounter platform in Reference Flow 7.0 allows designers to perform multiple mode/multiple corner timing closure, automatic decoupling capacitor insertion, and dynamic IR analysis, taking into account all power optimization modes.
lements of the Encounter platform within Reference Flow 7.0 include Encounter RTL Compiler global synthesis, Encounter Test, SoC Encounter system, Cadence QRC Extraction, VoltageStorm® Dynamic Gate power rail analysis, and CeltIC® Nanometer Delay Calculator (NDC), which work together to deliver high quality of silicon (QoS), improved timing closure, and reduced area.
Cadence SoC Encounter Global Physical Synthesis (GPS), which is included in Reference Flow 7.0, continues to provide solutions for critical manufacturing issues in the IC design process such as wire spreading, double-cut via optimization and metal fill. SoC Encounter GPS can automatically insert metal fill into a placed and routed design to achieve a metal density within the range recommended by TSMC design rules. It also enables automated wire-spreading and double-cut (dual) via insertion, which positively impact yield.
New capabilities in Reference Flow 7.0 include recommended DRC rule routing, half-track wire spreading, and critical area analysis (CAA). CAA analyzes wire density in a design vs. defect rate/size to derive maximum theoretical yield. SoC Encounter DFY™ has been certified by TSMC as DFM compliant for CAA.
With Reference Flow 7.0, the Cadence Allegro platform continues the tradition of improving chip/package integration in TSMC Reference Flows such as the new capability of handling simultaneous switching outputs in timing and IR drop analysis. The flow also includes the capabilities to estimate the ratio of signal to power and ground bumps, estimate the number of vias needed on multiple planes in the package and estimate the number of decoupling capacitors needed in the package.
DFT and True-Time Delay Test
Encounter Test has been validated by TSMC in Reference Flow 7.0 to address at- speed and power-aware ATPG, at speed-and faster-than-at-speed test, and ATPG test compression. At 90 nanometers and below, test vectors themselves can cause dynamic IR drop issues during test - indistinguishable at first glance from a failed chip. Power-aware test allows an understanding of the magnitude and sources of power consumption via toggles in scan flops - thus permitting both re-architecture of test patterns to avoid problems and allowing scan-flop-specific optimization to reduce power impact. Faster-than-at-speed test allows testing of the design with a throughput higher than the tester clock rate, while ATPG test compression uses on-board logic to reduce the number of pins and tester-applied vectors needed to achieve test coverage.
Statistical Static Timing Analysis (SSTA)
A new capability in Reference Flow 7.0 and the Encounter platform is statistical static timing analysis (SSTA) which uses a statistical distribution of cell timing/interconnect variance to determine the statistical distribution of timing of paths as would be expected in silicon. Cadence QRC Extraction is used to extract parameterized RC as a function of process variations, improving the performance and accuracy for SSTA. Using the advanced statistical modeling capability of Virtuoso® Spectre® Circuit Simulator, the process variation information provided by TSMC is accurately simulated and then converted into statistical cell timing models by SignalStorm-LC for statistical timing analysis.
TSMC Reference Flow 7.0 is available through the Company's customer web site, TSMC Online, or by contacting any TSMC account manager.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 12-inch wafer fabs, five 8-inch fabs and one 6-inch wafer fab. TSMC also has substantial capacity commitments at its wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65-nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.