Cadence Works with STARC to Address 65 Nanometer DFM ChallengesSTARC and Cadence Develop Flow for STARC Members to Ensure Prevention, Detection, Correction and Optimization of Manufacturing Effects on DesignSAN JOSE, Calif., 10 Jul 2007
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced the availability of an advanced design flow to improve manufacturability and yield for 65 nanometer designs developed by STARC. The flow is based on the Cadence® Encounter® digital IC design platform and provides STARC member companies with integrated and enhanced design for manufacturing (DFM) and design for yield capabilities.
Cadence and STARC have been collaborating for over 15 months to provide member companies with this new set of DFM capabilities, by creating a flow using the Cadence Encounter® platform, including Cadence SoC Encounter® GXL RTL-to-GDSII system, Cadence Chip Optimizer, Cadence CMP Predictor, and Cadence QRC Extraction. The resulting flow delivers a comprehensive methodology to address 65 nanometer design issues while minimizing potential yield fall-out due to tighter manufacturing parameters and effects due to lithography and chemical mechanical planarization (CMP).
To improve the manufacturability and performance of the design, the collaboration delivers a flow that allows design teams at member companies to prevent, detect and correct for manufacturing effects to ensure improved yield, improved process windows and improved management of process variations.
The Cadence Encounter platform-based design flow uses the combination of Cadence Chip Optimizer and Encounter NanoRoute® nanometer router to enable defect-based yield optimization. By integrating Cadence CMP Predictor into the Encounter platform, designers can now predict thickness variability and drive metal fill and CMP hotspot detection/correction. Feeding this data into the Cadence QRC Extraction tool provides more accurate delay prediction. The Encounter platform addresses lithographic effects in three integrated steps: prevention, detection and correction, delivering lithography-aware routing and an interface to third-party lithography analysis tools for hot-spot detection and correction. STARC and Cadence worked with lithography analysis companies to optimize the lithography hot-spot detection and correction flow in Cadence SoC Encounter GXL.
"Through our collaboration with Cadence, we believe we can help our member companies address their most pressing DFM issues at 65 nanometers," said Nobuyuki Nishiguchi, Vice President and General Manager of Development Dept.-1 at STARC. "Because the flow is based on the integration of key DFM technologies into the Encounter platform, our member companies will be able to improve yield while still meeting aggressive power, performance and schedule requirements."
"Many of our key customers in Japan depend on STARC and Cadence to help address some of their most pressing design issues," said Eric Filseth, corporate vice president of marketing at Cadence. "Our work with STARC will allow them to deliver a comprehensive design flow that addresses the DFM challenges at 65 nanometers, and we look forward to similar collaborative efforts at 45 nanometers and beyond."
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Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com