Cadence Encounter Digital Technology Provides Ambarella With Big Improvements in Power, Performance and Area
Ambarella Gains 15% Performance Improvement as Well as Reduction in Power Consumption for a Complex 32nm Encoder/Transcoder SoC

SAN JOSE, Calif., 27 Jun 2012

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that Ambarella, a leader in low-power, high-definition video compression and image-processing solutions for consumer cameras and television broadcasting, realized significant improvements in power, performance and area on a recent 32-nanometer gigahertz SoC design by upgrading to the latest Cadence Encounter RTL-to-GDSII flow. Using the latest Encounter technology, version 11.1, Ambarella saw a 15 percent improvement in performance and a 6.4 percent reduction in power consumption over the prior Cadence technology when designing the encoder/transcoder SoC.

“The complete Cadence Encounter RTL-to-GDSII flow allowed us to tape out a complex 32-nanometer SoC design and achieve significant and meaningful improvements in power, performance and area,” said Chan Lee, vice president of VLSI engineering at Ambarella. “The Clock Concurrent Optimization (CCOpt) technology alone saved us weeks of manual work by allowing us to optimize clocks and datapaths at the same time, while still delivering excellent results in power, performance, and area.”

Ambarella was able to concurrently optimize the initial netlist for power, performance and area using RTL Compiler’s global synthesis approach, which enabled a predictable handoff to EDI System implementation. The new GigaOpt optimization engine inside EDI System produces results faster than traditional optimization engines by harnessing the power of multiple CPUs. In addition, the CCOpt technology unifies clock tree synthesis with logic/physical optimization, resulting in significant power, performance and area improvements. When joined with the integrated signoff-proven QRC Extraction and Encounter Timing System, the full benefits of CCOpt timing optimization are maximized by eliminating timing correlation ECOs, improving time to tapeout.

“Cadence is committed to technology leadership and deep collaborations with foundries and IP providers to enable customers like Ambarella to succeed in very competitive markets,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “The Encounter RTL-to-GDSII flow, with many of the latest advanced technologies, enables Ambarella to hit market windows with high-quality products.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com


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