Casio Selects Cadence C-to-Silicon Compiler for High-Level SynthesisElectronics Giant Finds Great Productivity, Predictability and IP Reuse Benefits by Combining C-to-Silicon Compiler with Cadence RTL Compiler and Incisive Enterprise SimulatorSAN JOSE, Calif., 08 Jun 2009
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Casio Computer Co., Ltd., has selected the Cadence® C-to-Silicon Compiler
as its high-level synthesis solution. After a series of comprehensive benchmarks, Casio selected the Cadence solution over other industry products, citing the superior quality of results and predictability from C-to-Silicon Compiler.
C-to-Silicon Compiler is at the center of the Cadence next-generation TLM-based system-level design and verification solution. This solution combines Encounter® RTL Compiler
, Incisive® Enterprise Simulator
and C-to-Silicon Compiler to provide Casio an efficient, effective design and verification flow for mixed control and datapath designs, starting from SystemC, all the way to logic-gates.
“We conducted extensive testing to determine which technologies could meet our requirements and help us improve design and verification productivity,” said Kazuyuki Kurosawa, section manager, QV Digital Camera Division, Casio Computer Co., Ltd. “When we analyzed the results, we determined the C-to-Silicon Compiler, combined with the other Cadence technologies, were the strongest competitive offerings in the market. We are confident these will save us development time and reduce the risk of respins.”
C-to-Silicon Compiler high-level synthesis with embedded RTL Compiler enabled Casio engineers to produce IP with smaller area compared to the original RTL design. The combination of Incisive Enterprise Simulator (IES) with C-to-Silicon Compiler’s ability to automatically generate a SystemC wrapper for RTL verification using IES, enabled Casio to realize a seamless verification flow from SystemC to RTL.
“We recognized that a company like Casio, having a large IP portfolio, could benefit greatly from the increased designer productivity and IP reuse automation delivered by Cadence,” said Ran Avinun, System Design and Verification Product and Solutions Marketing Group Director of Cadence. “We’re pleased that Casio’s extensive benchmarking efforts drew the same conclusion, and joined to the rapidly growing list of new customers using C-to-Silicon Compiler.”
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Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com