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Virage Logic and Cadence Further Enable Low-Power Design
Cadence Low-Power Encounter Digital IC Design Flow Now Supports IPrima Mobile Platform Cell Library from Virage Logic for Significant Power Savings

SAN JOSE, Calif. and FREMONT, Calif., 08 Jun 2005

Cadence Design Systems, Inc. (NYSE: CDN) (Nasdaq: CDN) and Virage Logic Corporation (Nasdaq:VIRL) today announced that the CadenceĀ® Encounter™ low-power digital IC design flow now supports power saving features of Virage Logic's IPrima Mobile™ Semiconductor IP Platform's Ultra-Low-Power (ULP) standard cell library. This enables a low-power methodology that features full support of offset biasing, a substrate bias technique that can reduce device leakage up to 3.5 times. Cadence is the first EDA vendor to validate support of this technique for standard cell logic, which provides a proven path for offset bias rail routing and tap insertion methodologies.

Power leakage is a serious problem in cell-based digital designs, particularly at 90-nanometer technology nodes and below. Now, customers are able to utilize the full capabilities of Encounter IC implementation for producing leading-edge system-on-chip (SoC) designs with all of Virage Logic's Area, Speed and Power (ASAP) Logic™ and IPrima Mobile cell libraries in a fully validated design flow. The methodology validates how a designer can trade off performance with power through the use of an offset bias voltage source providing up to 3.5 times savings in leakage power. The Encounter low-power digital IC flow performs the routing of the additional bias rail and selects the proper tap option that enables the offset biasing option of the IPrima Mobile ULP cell library.

"Encounter is the first routing technology to demonstrate the Virage Logic IPrima Mobile Platform ULP cell library low-power offset biasing options," said Brani Buric, senior director of business development and platform product marketing at Virage Logic. "Although offset biasing is not new to the industry in terms of providing leakage power savings, this proven methodology is unique in addressing biasing capabilities at the SoC design level."

"This is an important follow-on to our news last February about our low-power design collaboration with Virage Logic," said Wei-Jin Dai, platform vice president, digital IC implementation at Cadence. "As Encounter continues to advance its technological capabilities, we can work with our mutual customers to address the continuing evolution of advanced techniques required in low-power design."

Virage Logic is a member of the OpenChoice IP Program which enables interoperability and facilitates open collaboration with IP providers to build, validate, and deliver accurate models optimized for Cadence design and verification solutions. The program aims to ensure IP quality and provide the semiconductor industry with access to critical IP through a complete IP catalog. This optimizes the electronics design chain and accelerates customer time to market.

About Virage Logic's IPrima Mobile Platform
As the first of Virage Logic's application-optimized semiconductor IP platforms, IPrima Mobile is targeted for hand-held and portable low-power system-on-chip (SoC) applications. Architected to extend battery life in low-power designs, the integrated IPrima Mobile Platform is comprised of Area, Speed and Power (ASAP) Memory Ultra-Low-Power (ULP) compilers, ASAP Logic ULP standard cells and Base I/O libraries. Based on more than five years of silicon-proven low-power IP expertise, IPrima Mobile provides up to 40 times leakage-power savings providing full operational, Active Low Power (ALP) and standby/sleep modes with state retention.

About Virage Logic Corporation
Founded in 1996, Virage Logic Corporation (Nasdaq:VIRL) rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Today the company is a global leader in semiconductor IP platforms comprising embedded memories, standard cells, and I/Os and is pioneering the development of a new class of IP called Silicon Aware IP. Silicon Aware IP tightly integrates Physical IP (memory, logic and I/Os) with the embedded test, diagnostic, and repair capabilities of Infrastructure IP to help ensure manufacturability and optimized yield at the advanced process nodes. Virage Logic's highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated-device manufacturers (IDMs) and fabless customers who develop products for the consumer, communications and networking, hand-held and portable, and computer and graphics markets. The company's comprehensive quality efforts are validated in its FirstPass-Silicon Characterization Lab, which helps ensure high quality, reliable IP across a wide range of foundries and process technologies. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit www.viragelogic.com.

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 4,700 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

SAFE HARBOR STATEMENT FOR VIRAGE LOGIC UNDER THE PRIVATE SECURITIES LITIGATION REFORM ACT OF 1995:
Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to trends, business outlook, products, and customer relationships. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to forecast its business, including its revenue, income and order flow outlook; Virage Logic's ability to execute on its strategy to become a provider of semiconductor IP platforms; Virage Logic's ability to continue to develop new products and maintain and develop new relationships with third-party foundries and integrated device manufacturers; adoption of Virage Logic's technologies by semiconductor companies and increases or fluctuations in the demand for their products; the company's ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies; the company's ability to obtain royalty revenues from customers in addition to license fees, to receive accurate information necessary for calculating royalty revenues and to collect royalty revenues from customers; business and economic conditions generally and in the semiconductor industry in particular; competition in the market for semiconductor IP platforms; and other risks including those described in the company's Annual Report on Form 10-K for the period ended September 30, 2004, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic's website or from the SEC's website, and in news releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.

For more information, please contact:
Sabina Burns
direct:510.743.8115
Sabina.burns@viragelogic.com
Virage Logic
Judy Erkanat
direct:408.894.2302
jerkanat@cadence.com
Cadence Design Systems, Inc.


Cadence, the Cadence logo are registered trademarks, and Encounter and SoC Encounter are trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.