Cadence Delivers 50% Power Savings in Latest STARC Production FlowSTARCAD-21 First Production Flow Based on Cadence Encounter 4.2 Digital IC Design TechnologySAN JOSE, Calif., 08 Jun 2005
Cadence Design Systems, Inc. (NYSE: CDN) (Nasdaq: CDN) today announced that a new design production flow from Japan's Semiconductor Technology Academic Research Center (STARC), developed using Cadence technology, has delivered 50 percent reduction in power consumption on designs. The STARCAD-21 Cadence Flow Version 2.0 is the first production flow based on Cadence® Encounter 4.2 digital technology.
STARC engineers conducted intensive evaluations of the Encounter 4.2 digital IC design technology while developing this flow. They focused on checking low-power methodologies, Multi Supply Voltage and Multi Vth cell optimizations, a hierarchical flow using ILM, global synthesis, and a common timing engine.
"We are very pleased to release this new production flow based on Encounter 4.2. As we go deeper into the nanometer era, we see designers facing a mixture of problems which range over timing, signal integrity, area, power and manufacturability," said Nobu Nishiguchi, Senior Manager, Design Methodology Development Group of STARC. "Our evaluations have proven that this implementation flow, supported by Encounter 4.2, solves these problems concurrently under its continuous convergence concept. We expect many designers to take advantage of this flow."
STARCAD-21 incorporates leading-edge Cadence technologies including Encounter RTL Compiler, SoC Encounter Global Physical Synthesis (GPS) floor planning and placement and routing, and sign-off technology from Fire & Ice® QXC parasitic extraction, CeltIC® Nanometer Delay Calculator (NDC), and VoltageStorm® power analysis.
"Though we cannot disclose the name, one of STARC's clients has applied this implementation flow to its complex 90 nanometer chip design and ended up with first Silicon success in a short period of time," Nishiguchi said. "We are proud to say that this is why we call our flow a production flow."
"We are pleased that the speed, capacity and maturity of the Encounter platform provided STARC with the resulting power savings for this latest production flow," said Wei-Jin Dai, corporate vice president, digital IC implementation at Cadence. "With continued customer successes such as this, the Encounter platform further extends its lead in high-speed digital IC design. We appreciate STARC's contribution to the improved quality of Encounter 4.2 throughout its evaluation process as Cadence continues to take the complexity out of low power implementation."
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Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 4,700 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com